Merge remote-tracking branch 'origin/main' into bringup2

generators/chipyard/src/main/resources/csrc/cospike.cc

@@ -0,0 +1,258 @@
+#include <vector>
+#include <string>
+#include <riscv/sim.h>
+#include <vpi_user.h>
+#include <svdpi.h>
+#include <sstream>
+#include <set>
+
+#define CLINT_BASE (0x2000000)
+#define CLINT_SIZE (0x1000)
+
+typedef struct system_info_t {
+  std::string isa;
+  int pmpregions;
+  uint64_t mem0_base;
+  uint64_t mem0_size;
+  int nharts;
+  std::vector<char> bootrom;
+};
+
+system_info_t* info = NULL;
+sim_t* sim = NULL;
+reg_t tohost_addr = 0;
+reg_t fromhost_addr = 0;
+std::set<reg_t> magic_addrs;
+cfg_t* cfg;
+
+static std::vector<std::pair<reg_t, mem_t*>> make_mems(const std::vector<mem_cfg_t> &layout)
+{
+  std::vector<std::pair<reg_t, mem_t*>> mems;
+  mems.reserve(layout.size());
+  for (const auto &cfg : layout) {
+    mems.push_back(std::make_pair(cfg.get_base(), new mem_t(cfg.get_size())));
+  }
+  return mems;
+}
+
+extern "C" void cospike_set_sysinfo(char* isa, int pmpregions,
+                                    long long int mem0_base, long long int mem0_size,
+                                    int nharts,
+                                    char* bootrom
+                                    ) {
+  if (!info) {
+    info = new system_info_t;
+    info->isa = std::string(isa);
+    info->pmpregions = pmpregions;
+    info->mem0_base = mem0_base;
+    info->mem0_size = mem0_size;
+    info->nharts = nharts;
+    std::stringstream ss(bootrom);
+    std::string s;
+    while (ss >> s) {
+      info->bootrom.push_back(std::stoi(s));
+    }
+  }
+}
+
+extern "C" void cospike_cosim(long long int cycle,
+                              long long int hartid,
+                              int has_wdata,
+                              int valid,
+                              long long int iaddr,
+                              unsigned long int insn,
+                              int raise_exception,
+                              int raise_interrupt,
+                              unsigned long long int cause,
+                              unsigned long long int wdata)
+{
+  assert(info);
+  if (!sim) {
+    printf("Configuring spike cosim\n");
+    std::vector<mem_cfg_t> mem_cfg;
+    std::vector<int> hartids;
+    mem_cfg.push_back(mem_cfg_t(info->mem0_base, info->mem0_size));
+    for (int i = 0; i < info->nharts; i++)
+      hartids.push_back(i);
+
+    cfg = new cfg_t(std::make_pair(0, 0),
+                    nullptr,
+                    info->isa.c_str(),
+                    "MSU",
+                    "vlen:128,elen:64",
+                    false,
+                    endianness_little,
+                    info->pmpregions,
+                    mem_cfg,
+                    hartids,
+                    false,
+                    0
+                    );
+
+    std::vector<std::pair<reg_t, mem_t*>> mems = make_mems(cfg->mem_layout());
+
+    rom_device_t *boot_rom = new rom_device_t(info->bootrom);
+    mem_t *boot_addr_reg = new mem_t(0x1000);
+    uint64_t default_boot_addr = 0x80000000;
+    boot_addr_reg->store(0, 8, (const uint8_t*)(&default_boot_addr));
+
+    // Don't actually build a clint
+    mem_t* clint_mem = new mem_t(CLINT_SIZE);
+
+    std::vector<std::pair<reg_t, abstract_device_t*>> plugin_devices;
+    // The device map is hardcoded here for now
+    plugin_devices.push_back(std::pair(0x4000, boot_addr_reg));
+    plugin_devices.push_back(std::pair(0x10000, boot_rom));
+    plugin_devices.push_back(std::pair(CLINT_BASE, clint_mem));
+
+    s_vpi_vlog_info vinfo;
+    if (!vpi_get_vlog_info(&vinfo))
+      abort();
+    std::vector<std::string> htif_args;
+    bool in_permissive = false;
+    bool cospike_debug = false;
+    for (int i = 1; i < vinfo.argc; i++) {
+      std::string arg(vinfo.argv[i]);
+      if (arg == "+permissive") {
+        in_permissive = true;
+      } else if (arg == "+permissive-off") {
+        in_permissive = false;
+      } else if (arg == "+cospike_debug") {
+        cospike_debug = true;
+      } else if (!in_permissive) {
+        htif_args.push_back(arg);
+      }
+    }
+
+    debug_module_config_t dm_config = {
+      .progbufsize = 2,
+      .max_sba_data_width = 0,
+      .require_authentication = false,
+      .abstract_rti = 0,
+      .support_hasel = true,
+      .support_abstract_csr_access = true,
+      .support_abstract_fpr_access = true,
+      .support_haltgroups = true,
+      .support_impebreak = true
+    };
+
+    printf("%s\n", info->isa.c_str());
+    for (int i = 0; i < htif_args.size(); i++) {
+      printf("%s\n", htif_args[i].c_str());
+    }
+
+    sim = new sim_t(cfg, false,
+                    mems,
+                    plugin_devices,
+                    htif_args,
+                    dm_config,
+                    nullptr,
+                    false,
+                    nullptr,
+                    false,
+                    nullptr
+                    );
+
+    sim->configure_log(true, true);
+    // Use our own reset vector
+    for (int i = 0; i < info->nharts; i++) {
+      sim->get_core(hartid)->get_state()->pc = 0x10040;
+    }
+    sim->set_debug(cospike_debug);
+    printf("Setting up htif for spike cosim\n");
+    ((htif_t*)sim)->start();
+    printf("Spike cosim started\n");
+    tohost_addr = ((htif_t*)sim)->get_tohost_addr();
+    fromhost_addr = ((htif_t*)sim)->get_fromhost_addr();
+    printf("Tohost  : %lx\n", tohost_addr);
+    printf("Fromhost: %lx\n", fromhost_addr);
+  }
+
+  processor_t* p = sim->get_core(hartid);
+  state_t* s = p->get_state();
+  uint64_t s_pc = s->pc;
+  if (raise_interrupt) {
+    printf("%d interrupt %lx\n", cycle, cause);
+    uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF;
+    if (interrupt_cause == 3) {
+      s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP);
+    } else {
+      printf("Unknown interrupt %lx\n", interrupt_cause);
+    }
+  }
+  if (raise_exception)
+    printf("%d exception %lx\n", cycle, cause);
+  if (valid) {
+    printf("%d Cosim: %lx", cycle, iaddr);
+    if (has_wdata) {
+      printf(" %lx", wdata);
+    }
+    printf("\n");
+  }
+  if (valid || raise_interrupt || raise_exception)
+    p->step(1);
+
+  if (valid) {
+    if (s_pc != iaddr) {
+      printf("%d PC mismatch %lx != %lx\n", cycle, s_pc, iaddr);
+      exit(1);
+    }
+
+    // Try to remember magic_mem addrs, and ignore these in the future
+    auto& mem_write = s->log_mem_write;
+    if (!mem_write.empty() && tohost_addr && std::get<0>(mem_write[0]) == tohost_addr) {
+      reg_t wdata = std::get<1>(mem_write[0]);
+      if (wdata >= info->mem0_base && wdata < (info->mem0_base + info->mem0_size)) {
+        printf("Probable magic mem %x\n", wdata);
+        magic_addrs.insert(wdata);
+      }
+    }
+
+    if (has_wdata) {
+      auto& log = s->log_reg_write;
+      auto& mem_read = s->log_mem_read;
+      reg_t mem_read_addr = mem_read.empty() ? 0 : std::get<0>(mem_read[0]);
+      for (auto regwrite : log) {
+        int rd = regwrite.first >> 4;
+        int type = regwrite.first & 0xf;
+        // 0 => int
+        // 1 => fp
+        // 2 => vec
+        // 3 => vec hint
+        // 4 => csr
+        if ((rd != 0 && type == 0) || type == 1) {
+          // Override reads from some CSRs
+          uint64_t csr_addr = (insn >> 20) & 0xfff;
+          bool csr_read = (insn & 0x7f) == 0x73;
+          if (csr_read) printf("CSR read %lx\n", csr_addr);
+          if (csr_read && (
+                           (csr_addr == 0x301) || // misa
+                           (csr_addr == 0xf13) || // mimpid
+                           (csr_addr == 0xf12) || // marchid
+                           (csr_addr == 0xf11) || // mvendorid
+                           (csr_addr == 0xb00) || // mcycle
+                           (csr_addr == 0xb02) || // minstret
+                           (csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr
+                           )) {
+            printf("CSR override\n");
+            s->XPR.write(rd, wdata);
+          } else if (!mem_read.empty() && ((magic_addrs.count(mem_read_addr) ||
+					    (tohost_addr && mem_read_addr == tohost_addr) ||
+					    (fromhost_addr && mem_read_addr == fromhost_addr) ||
+					    (CLINT_BASE <= mem_read_addr && mem_read_addr < (CLINT_BASE + CLINT_SIZE))
+					    ))) {
+	    // Don't check reads from tohost, reads from magic memory, or reads from clint
+	    // Technically this could be buggy because log_mem_read only reports vaddrs, but
+	    // no software ever should access tohost/fromhost/clint with vaddrs anyways
+	    printf("Read override %lx\n", mem_read_addr);
+	    s->XPR.write(rd, wdata);
+          } else if (wdata != regwrite.second.v[0]) {
+	    printf("%d wdata mismatch reg %d %lx != %lx\n", cycle, rd, regwrite.second.v[0], wdata);
+	    exit(1);
+	  }
+	}
+      }
+    }
+  }
+}
+// }

generators/chipyard/src/main/resources/vsrc/cospike.v

@@ -0,0 +1,74 @@
+import "DPI-C" function void cospike_set_sysinfo(
+						 input string  isa,
+						 input int     pmpregions,
+						 input longint mem0_base,
+						 input longint mem0_size,
+						 input int     nharts,
+						 input string  bootrom
+						 );
+
+import "DPI-C" function void cospike_cosim(input longint cycle,
+                                           input longint hartid,
+					   input bit	 has_wdata,
+					   input bit	 valid,
+					   input longint iaddr,
+					   input int	 insn,
+					   input bit	 raise_exception,
+					   input bit	 raise_interrupt,
+					   input longint cause,
+					   input longint wdata
+					   );
+
+
+module SpikeCosim  #(
+		     parameter ISA,
+		     parameter PMPREGIONS,
+		     parameter MEM0_BASE,
+		     parameter MEM0_SIZE,
+		     parameter NHARTS,
+		     parameter BOOTROM) (
+					 input	      clock,
+					 input	      reset,
+
+					 input [63:0] cycle,
+
+					 input [63:0] hartid,
+
+					 input	      trace_0_valid,
+					 input [63:0] trace_0_iaddr,
+					 input [31:0] trace_0_insn,
+					 input	      trace_0_exception,
+					 input	      trace_0_interrupt,
+					 input [63:0] trace_0_cause,
+					 input	      trace_0_has_wdata,
+					 input [63:0] trace_0_wdata,
+
+					 input	      trace_1_valid,
+					 input [63:0] trace_1_iaddr,
+					 input [31:0] trace_1_insn,
+					 input	      trace_1_exception,
+					 input	      trace_1_interrupt,
+					 input [63:0] trace_1_cause,
+					 input	      trace_1_has_wdata,
+					 input [63:0] trace_1_wdata
+					 );
+
+   initial begin
+      cospike_set_sysinfo(ISA, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
+   end;
+
+   always @(posedge clock) begin
+      if (!reset) begin
+	 if (trace_0_valid || trace_0_exception || trace_0_cause) begin
+	    cospike_cosim(cycle, hartid, trace_0_has_wdata, trace_0_valid, trace_0_iaddr,
+			  trace_0_insn, trace_0_exception, trace_0_interrupt, trace_0_cause,
+			  trace_0_wdata);
+	 end
+	 if (trace_1_valid || trace_1_exception || trace_1_cause) begin
+	    cospike_cosim(cycle, hartid, trace_1_has_wdata, trace_1_valid, trace_1_iaddr,
+			  trace_1_insn, trace_1_exception, trace_1_interrupt, trace_1_cause,
+			  trace_1_wdata);
+	 end
+      end
+   end
+endmodule; // CospikeCosim

generators/chipyard/src/main/scala/Cospike.scala

@@ -0,0 +1,88 @@
+package chipyard
+
+import chisel3._
+import chisel3.experimental.{IntParam, StringParam, IO}
+import chisel3.util._
+
+import freechips.rocketchip.config.{Parameters, Field, Config}
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.util._
+
+import testchipip.TileTraceIO
+
+case class SpikeCosimConfig(
+  isa: String,
+  pmpregions: Int,
+  mem0_base: BigInt,
+  mem0_size: BigInt,
+  nharts: Int,
+  bootrom: String
+)
+
+class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map(
+  "ISA" -> StringParam(cfg.isa),
+  "PMPREGIONS" -> IntParam(cfg.pmpregions),
+  "MEM0_BASE" -> IntParam(cfg.mem0_base),
+  "MEM0_SIZE" -> IntParam(cfg.mem0_size),
+  "NHARTS" -> IntParam(cfg.nharts),
+  "BOOTROM" -> StringParam(cfg.bootrom)
+)) with HasBlackBoxResource
+{
+  addResource("/csrc/cospike.cc")
+  addResource("/vsrc/cospike.v")
+  val io = IO(new Bundle {
+    val clock = Input(Clock())
+    val reset = Input(Bool())
+    val cycle = Input(UInt(64.W))
+    val hartid = Input(UInt(64.W))
+    val trace = Input(Vec(2, new Bundle {
+      val valid = Bool()
+      val iaddr = UInt(64.W)
+      val insn = UInt(32.W)
+      val exception = Bool()
+      val interrupt = Bool()
+      val cause = UInt(64.W)
+      val has_wdata = Bool()
+      val wdata = UInt(64.W)
+    }))
+  })
+}
+
+object SpikeCosim
+{
+  def apply(trace: TileTraceIO, hartid: Int, cfg: SpikeCosimConfig) = {
+    val cosim = Module(new SpikeCosim(cfg))
+    val cycle = withClockAndReset(trace.clock, trace.reset) {
+      val r = RegInit(0.U(64.W))
+      r := r + 1.U
+      r
+    }
+    cosim.io.clock := trace.clock
+    cosim.io.reset := trace.reset
+    require(trace.numInsns <= 2)
+    cosim.io.cycle := cycle
+    cosim.io.trace.map(t => {
+      t.valid := false.B
+      t.iaddr := 0.U
+      t.insn := 0.U
+      t.exception := false.B
+      t.interrupt := false.B
+      t.cause := 0.U
+    })
+    cosim.io.hartid := hartid.U
+    for (i <- 0 until trace.numInsns) {
+      cosim.io.trace(i).valid := trace.insns(i).valid
+      val signed = Wire(SInt(64.W))
+      signed := trace.insns(i).iaddr.asSInt
+      cosim.io.trace(i).iaddr := signed.asUInt
+      cosim.io.trace(i).insn := trace.insns(i).insn
+      cosim.io.trace(i).exception := trace.insns(i).exception
+      cosim.io.trace(i).interrupt := trace.insns(i).interrupt
+      cosim.io.trace(i).cause := trace.insns(i).cause
+      cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B
+      cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U)
+    }
+  }
+}

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -21,7 +21,7 @@ import barstools.iocell.chisel._
 
 import testchipip._
 
-import chipyard.{HasHarnessSignalReferences, HarnessClockInstantiatorKey}
+import chipyard._
 import chipyard.clocking.{HasChipyardPRCI}
 import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, ClockWithFreq}
 
@@ -354,6 +354,24 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({
   }
 })
 
+class WithCospike extends ComposeHarnessBinder({
+  (system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => {
+    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
+    val tiles = chipyardSystem.tiles
+    val cfg = SpikeCosimConfig(
+      isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
+      mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
+      mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
+      pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
+      nharts = tiles.size,
+      bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("")
+    )
+    ports.map { p => p.traces.zipWithIndex.map(t => SpikeCosim(t._1, t._2, cfg)) }
+  }
+})
+
+
 class WithCustomBootPinPlusArg extends OverrideHarnessBinder({
   (system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => {
     val pin = PlusArg("custom_boot_pin", width=1)

generators/chipyard/src/main/scala/SpikeTile.scala

@@ -16,7 +16,6 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.prci.ClockSinkParameters
 
 case class SpikeCoreParams(
-  val maxInsnsPerCycle: Int = 10000
 ) extends CoreParams {
   val useVM = true
   val useHypervisor = false
@@ -305,23 +304,29 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   spike.io.msip := int_bundle.msip
   spike.io.meip := int_bundle.meip
   spike.io.seip := int_bundle.seip.get
-  spike.io.ipc := outer.spikeTileParams.core.maxInsnsPerCycle.U
+  spike.io.ipc := PlusArg("spike-ipc", 10000, width=64)
 
   val blockBits = log2Ceil(p(CacheBlockBytes))
-  spike.io.icache.a.ready := icache_tl.a.ready
-  icache_tl.a.valid := spike.io.icache.a.valid
-  icache_tl.a.bits := icacheEdge.Get(
+
+  val icache_a_q = Module(new Queue(new TLBundleA(icacheEdge.bundle), 1, flow=true, pipe=true))
+  spike.io.icache.a.ready := icache_a_q.io.enq.ready && icache_a_q.io.count === 0.U
+  icache_tl.a <> icache_a_q.io.deq
+  icache_a_q.io.enq.valid := spike.io.icache.a.valid
+  icache_a_q.io.enq.bits := icacheEdge.Get(
     fromSource = spike.io.icache.a.sourceid,
     toAddress = (spike.io.icache.a.address >> blockBits) << blockBits,
     lgSize = blockBits.U)._2
+
   icache_tl.d.ready := true.B
   spike.io.icache.d.valid := icache_tl.d.valid
   spike.io.icache.d.sourceid := icache_tl.d.bits.source
   spike.io.icache.d.data := icache_tl.d.bits.data.asTypeOf(Vec(8, UInt(64.W)))
 
-  spike.io.dcache.a.ready := dcache_tl.a.ready
-  dcache_tl.a.valid := spike.io.dcache.a.valid
-  dcache_tl.a.bits := dcacheEdge.AcquireBlock(
+  val dcache_a_q = Module(new Queue(new TLBundleA(dcacheEdge.bundle), 1, flow=true, pipe=true))
+  spike.io.dcache.a.ready := dcache_a_q.io.enq.ready && dcache_a_q.io.count === 0.U
+  dcache_tl.a <> dcache_a_q.io.deq
+  dcache_a_q.io.enq.valid := spike.io.dcache.a.valid
+  dcache_a_q.io.enq.bits := dcacheEdge.AcquireBlock(
     fromSource = spike.io.dcache.a.sourceid,
     toAddress = (spike.io.dcache.a.address >> blockBits) << blockBits,
     lgSize = blockBits.U,
@@ -333,9 +338,11 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   spike.io.dcache.b.source := dcache_tl.b.bits.source
   spike.io.dcache.b.param := dcache_tl.b.bits.param
 
-  spike.io.dcache.c.ready := dcache_tl.c.ready
-  dcache_tl.c.valid := spike.io.dcache.c.valid
-  dcache_tl.c.bits := Mux(spike.io.dcache.c.voluntary,
+  val dcache_c_q = Module(new Queue(new TLBundleC(dcacheEdge.bundle), 1, flow=true, pipe=true))
+  spike.io.dcache.c.ready := dcache_c_q.io.enq.ready && dcache_c_q.io.count === 0.U
+  dcache_tl.c <> dcache_c_q.io.deq
+  dcache_c_q.io.enq.valid := spike.io.dcache.c.valid
+  dcache_c_q.io.enq.bits := Mux(spike.io.dcache.c.voluntary,
     dcacheEdge.Release(
       fromSource = spike.io.dcache.c.sourceid,
       toAddress = spike.io.dcache.c.address,
@@ -369,10 +376,12 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   dcache_tl.e.valid := dcache_tl.d.valid && should_finish
   dcache_tl.e.bits := dcacheEdge.GrantAck(dcache_tl.d.bits)
 
-  spike.io.mmio.a.ready := mmio_tl.a.ready
-  mmio_tl.a.valid := spike.io.mmio.a.valid
+  val mmio_a_q = Module(new Queue(new TLBundleA(mmioEdge.bundle), 1, flow=true, pipe=true))
+  spike.io.mmio.a.ready := mmio_a_q.io.enq.ready && mmio_a_q.io.count === 0.U
+  mmio_tl.a <> mmio_a_q.io.deq
+  mmio_a_q.io.enq.valid := spike.io.mmio.a.valid
   val log_size = MuxCase(0.U, (0 until 3).map { i => (spike.io.mmio.a.size === (1 << i).U) -> i.U })
-  mmio_tl.a.bits := Mux(spike.io.mmio.a.store,
+  mmio_a_q.io.enq.bits := Mux(spike.io.mmio.a.store,
     mmioEdge.Put(0.U, spike.io.mmio.a.address, log_size, spike.io.mmio.a.data)._2,
     mmioEdge.Get(0.U, spike.io.mmio.a.address, log_size)._2)
 

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -52,6 +52,7 @@ class AbstractConfig extends Config(
   new chipyard.config.WithPeripheryBusFrequencyAsDefault ++         // Unspecified frequencies with match the pbus frequency (which is always set)
   new chipyard.config.WithMemoryBusFrequency(100.0) ++              // Default 100 MHz mbus
   new chipyard.config.WithPeripheryBusFrequency(100.0) ++           // Default 100 MHz pbus
+  new freechips.rocketchip.subsystem.WithClockGateModel ++          // add default EICG_wrapper clock gate model
   new freechips.rocketchip.subsystem.WithJtagDTM ++                 // set the debug module to expose a JTAG port
   new freechips.rocketchip.subsystem.WithNoMMIOPort ++              // no top-level MMIO master port (overrides default set in rocketchip)
   new freechips.rocketchip.subsystem.WithNoSlavePort ++             // no top-level MMIO slave port (overrides default set in rocketchip)

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -47,3 +47,9 @@ class DromajoBoomConfig extends Config(
   new boom.common.WithNSmallBooms(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
+
+class MediumBoomCosimConfig extends Config(
+  new chipyard.harness.WithCospike ++                            // attach spike-cosim
+  new chipyard.config.WithTraceIO ++                             // enable the traceio
+  new boom.common.WithNMediumBooms(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala

@@ -56,3 +56,11 @@ class LargeNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("large", true) ++         // add a large NVDLA with synth. rams
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
+
+class ManyMMIOAcceleratorRocketConfig extends Config(
+  new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
+  new nvidia.blocks.dla.WithNVDLA("small") ++               // add a small NVDLA
+  new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
+  new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -63,3 +63,15 @@ class dmiRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DmiRocket
+
+class ManyPeripheralsRocketConfig extends Config(
+  new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
+  new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
+  new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
+  new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
+  new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
+  new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
+  new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
+  new freechips.rocketchip.subsystem.WithNoMemPort ++        // remove AXI4 backing memory
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -9,7 +9,6 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
 
 import boom.common.{BoomTileAttachParams}
 import cva6.{CVA6TileAttachParams}
-
 import testchipip._
 
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -79,3 +78,4 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
     ))
   }
 })
+

generators/chipyard/src/main/scala/example/InitZero.scala

@@ -5,14 +5,14 @@ import chisel3.util._
 import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
-import testchipip.TLHelper
+import freechips.rocketchip.tilelink._
 
 case class InitZeroConfig(base: BigInt, size: BigInt)
 case object InitZeroKey extends Field[Option[InitZeroConfig]](None)
 
 class InitZero(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode(
-    name = "init-zero", sourceId = IdRange(0, 1))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
+    name = "init-zero", sourceId = IdRange(0, 1))))))
 
   lazy val module = new InitZeroModuleImp(this)
 }

generators/chipyard/src/main/scala/example/NodeTypes.scala

@@ -3,7 +3,6 @@ package chipyard.example
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import testchipip.TLHelper
 
 // These modules are not meant to be synthesized.
 // They are used as examples in the documentation and are only here
@@ -11,11 +10,11 @@ import testchipip.TLHelper
 
 // DOC include start: MyClient
 class MyClient(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode(TLMasterParameters.v1(
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
     name = "my-client",
     sourceId = IdRange(0, 4),
     requestFifo = true,
-    visibility = Seq(AddressSet(0x10000, 0xffff))))
+    visibility = Seq(AddressSet(0x10000, 0xffff)))))))
 
   lazy val module = new LazyModuleImp(this) {
     val (tl, edge) = node.out(0)
@@ -29,7 +28,7 @@ class MyClient(implicit p: Parameters) extends LazyModule {
 class MyManager(implicit p: Parameters) extends LazyModule {
   val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
   val beatBytes = 8
-  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
     address = Seq(AddressSet(0x20000, 0xfff)),
     resources = device.reg,
     regionType = RegionType.UNCACHED,
@@ -40,7 +39,7 @@ class MyManager(implicit p: Parameters) extends LazyModule {
     supportsPutFull = TransferSizes(1, beatBytes),
     supportsPutPartial = TransferSizes(1, beatBytes),
     supportsHint = TransferSizes(1, beatBytes),
-    fifoId = Some(0)))
+    fifoId = Some(0))), beatBytes)))
 
   lazy val module = new LazyModuleImp(this) {
     val (tl, edge) = node.in(0)
@@ -50,7 +49,8 @@ class MyManager(implicit p: Parameters) extends LazyModule {
 
 // DOC include start: MyClient1+MyClient2
 class MyClient1(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode("my-client1", IdRange(0, 1))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
+    "my-client1", IdRange(0, 1))))))
 
   lazy val module = new LazyModuleImp(this) {
     // ...
@@ -58,7 +58,8 @@ class MyClient1(implicit p: Parameters) extends LazyModule {
 }
 
 class MyClient2(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode("my-client2", IdRange(0, 1))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
+    "my-client2", IdRange(0, 1))))))
 
   lazy val module = new LazyModuleImp(this) {
     // ...
@@ -83,8 +84,8 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule {
 
 // DOC include start: MyManagerGroup
 class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
-    address = Seq(AddressSet(0x0, 0xfff))))
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
+    address = Seq(AddressSet(0x0, 0xfff)))), beatBytes)))
 
   lazy val module = new LazyModuleImp(this) {
     // ...
@@ -92,8 +93,8 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
-    address = Seq(AddressSet(0x1000, 0xfff))))
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
+    address = Seq(AddressSet(0x1000, 0xfff)))), beatBytes)))
 
   lazy val module = new LazyModuleImp(this) {
     // ...