Share DigitalTop/ChipyardSystem | Fix small naming compile error

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -20,6 +20,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
+  with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
   with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
@@ -35,6 +36,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
   with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
   with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp
   with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp
+  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
   with chipyard.example.CanHavePeripheryGCDModuleImp
   with freechips.rocketchip.util.DontTouch
 // DOC include end: DigitalTop

generators/chipyard/src/main/scala/System.scala

@@ -7,7 +7,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
@@ -23,7 +23,8 @@ import freechips.rocketchip.util.{DontTouch}
  */
 class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
   with HasAsyncExtInterrupts
-  with CanHaveMasterAXI4MemPort
+  with CanHaveMasterTLMemPort // export TL port for outer memory
+  with CanHaveMasterAXI4MemPort // expose AXI port for outer mem
   with CanHaveMasterAXI4MMIOPort
   with CanHaveSlaveAXI4Port
 {
@@ -40,3 +41,46 @@ class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubs
   with HasRTCModuleImp
   with HasExtInterruptsModuleImp
   with DontTouch
+
+// ------------------------------------
+// TL Mem Port Mixin
+// ------------------------------------
+
+// Similar to ExtMem but instantiates a TL mem port
+case object ExtTLMem extends Field[Option[MemoryPortParams]](None)
+
+/** Adds a port to the system intended to master an TL DRAM controller. */
+trait CanHaveMasterTLMemPort { this: BaseSubsystem =>
+  private val memPortParamsOpt = p(ExtTLMem)
+  private val portName = "tl_mem"
+  private val device = new MemoryDevice
+  private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+
+  val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels) =>
+    Seq.tabulate(nMemoryChannels) { channel =>
+      val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
+      val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
+
+     TLSlavePortParameters.v1(
+       managers = Seq(TLSlaveParameters.v1(
+         address            = base.flatMap(_.intersect(filter)),
+         resources          = device.reg,
+         regionType         = RegionType.UNCACHED, // cacheable
+         executable         = true,
+         supportsGet        = TransferSizes(1, mbus.blockBytes),
+         supportsPutFull    = TransferSizes(1, mbus.blockBytes),
+         supportsPutPartial = TransferSizes(1, mbus.blockBytes))),
+         beatBytes = memPortParams.beatBytes)
+   }
+ }).toList.flatten)
+
+ mbus.coupleTo(s"memory_controller_port_named_$portName") {
+   (memTLNode
+     :*= TLBuffer()
+     :*= TLSourceShrinker(1 << idBits)
+     :*= TLWidthWidget(mbus.beatBytes)
+     :*= _)
+  }
+
+  val mem_tl = InModuleBody { memTLNode.makeIOs() }
+}