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Share DigitalTop/ChipyardSystem | Fix small naming compile error

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This commit is contained in:
abejgonzalez
2020-11-23 15:46:03 -08:00
parent 95e8365105
commit 661a7701a7
9 changed files with 63 additions and 117 deletions
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6
fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
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@@ -9,18 +9,18 @@ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule}
import chipyard.{DigitalTop, DigitalTopModule}
// ------------------------------------
// Bringup VCU118 DigitalTop
// ------------------------------------
class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop
class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
with sifive.blocks.devices.i2c.HasPeripheryI2C
with testchipip.HasPeripheryTSIHostWidget
{
override lazy val module = new BringupVCU118DigitalTopModule(this)
}
class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends VCU118DigitalTopModule(l)
class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l)
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp