wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Share DigitalTop/ChipyardSystem | Fix small naming compile error

Browse Source
This commit is contained in:
abejgonzalez
2020-11-23 15:46:03 -08:00
parent 95e8365105
commit 661a7701a7
9 changed files with 63 additions and 117 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -17,7 +17,7 @@ import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.gpio._
import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop}
import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, ChipTop, ExtTLMem, CanHaveMasterTLMemPort}
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness.{ApplyHarnessBinders}
@@ -79,7 +79,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
/*** DDR ***/
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr
// connect 1 mem. channel to the FPGA DDR
val inParams = topDesign match { case td: ChipTop =>