Share DigitalTop/ChipyardSystem | Fix small naming compile error

2020-11-23 15:46:03 -08:00
parent 95e8365105
commit 661a7701a7
9 changed files with 63 additions and 117 deletions
--- a/fpga/src/main/scala/vcu118/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
 import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}

-import chipyard.{HasHarnessSignalReferences}
+import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort}
 import chipyard.harness.{OverrideHarnessBinder}

 /*** UART ***/