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Share DigitalTop/ChipyardSystem | Fix small naming compile error

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abejgonzalez
2020-11-23 15:46:03 -08:00
parent 95e8365105
commit 661a7701a7
9 changed files with 63 additions and 117 deletions
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fpga/src/main/scala/arty/Configs.scala
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@@ -31,7 +31,7 @@ class WithArtyTweaks extends Config(
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
new WithArtyResetHarnessBinder ++
new WithResetPassthrough ++
new WithDebugResetPassthrough ++
new WithDefaultPeripherals ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory