Make FPGA flows use the harnessClockInstantiator

2023-05-11 13:03:47 -07:00
parent a9bc11accb
commit 64ad77bbcf
9 changed files with 43 additions and 1 deletions
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -21,7 +21,7 @@ class WithArtyTweaks extends Config(
  new WithArtyJTAGHarnessBinder ++
  new WithArtyUARTHarnessBinder ++
  new WithDebugResetPassthrough ++
-
+  new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
  new chipyard.config.WithDTSTimebase(32768) ++
  new testchipip.WithNoSerialTL
 )