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Small renaming/cleanup | Use LinkedHashMaps

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abejgonzalez
2021-03-15 16:54:42 -07:00
parent 30c9b63e7b
commit 6476c7e7f0
9 changed files with 43 additions and 56 deletions
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11
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -110,21 +110,14 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
implicit val p = GetSystemParameters(system)
p(SerialTLKey).map({ sVal =>
// currently only the harness AXI port supports a passthrough clock
require(sVal.axiMemOverSerialTLParams.isDefined)
val axiDomainParams = sVal.axiMemOverSerialTLParams.get
require(sVal.isMemoryDevice)
val memFreq: Double = axiDomainParams.axiClockParams match {
case Some(clkParams) => clkParams.clockFreqMHz * 1000000
case None => {
// get freq. from what the master of the serial link specifies
system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(p(SerialTLAttachKey).masterWhere).dtsFrequency.get.toDouble
}
}
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
ports.map({ port =>
val axiClock = p(ClockBridgeInstantiatorKey).getClock("mem_over_serial_tl_clock", memFreq)
val axiClock = p(ClockBridgeInstantiatorKey).requestClock("mem_over_serial_tl_clock", memFreq)
val axiClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
axiClockBundle.clock := axiClock
axiClockBundle.reset := ResetCatchAndSync(axiClock, th.harnessReset.asBool)