Small renaming/cleanup | Use LinkedHashMaps

generators/chipyard/src/main/scala/Clocks.scala

@@ -86,7 +86,7 @@ object ClockingSchemeGenerators {
       :*= aggregator)
 
     val referenceClockSource =  ClockSourceNode(Seq(ClockSourceParameters()))
-    val dividerOnlyClkGenerator = DividerOnlyClockGenerator()
+    val dividerOnlyClkGenerator = LazyModule(new DividerOnlyClockGenerator("buildTopClockGenerator"))
     // provides all the divided clocks (from the top-level clock)
     (aggregator
       := ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -217,6 +217,12 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
   )}
 })
 
+/**
+  * Mixins to define either a specific tile frequency for a single hart or all harts
+  *
+  * @param fMHz Frequency in MHz of the tile or all tiles
+  * @param hartId Optional hartid to assign the frequency to (if unspecified default to all harts)
+  */
 class WithTileFrequency(fMHz: Double, hartId: Option[Int] = None) extends ClockNameContainsAssignment({
     hartId match {
       case Some(id) => s"tile_$id"

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -144,21 +144,15 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
 
     p(SerialTLKey).map({ sVal =>
-      // currently only the harness AXI port supports a passthrough clock
       require(sVal.axiMemOverSerialTLParams.isDefined)
       val axiDomainParams = sVal.axiMemOverSerialTLParams.get
+      require(sVal.isMemoryDevice)
 
-      val memFreq: Double = axiDomainParams.axiClockParams match {
-        case Some(clkParams) => clkParams.clockFreqMHz * 1000000
-        case None => {
-          // get freq. from what the master of the serial link specifies
-          system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(p(SerialTLAttachKey).masterWhere).dtsFrequency.get.toDouble
-        }
-      }
+      val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
 
       ports.map({ port =>
 // DOC include start: HarnessClockInstantiatorEx
-        val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).getClockBundle("mem_over_serial_tl_clock", memFreq)
+        val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).requestClockBundle("mem_over_serial_tl_clock", memFreq)
         val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
           system.serdesser.get,
           port,

generators/chipyard/src/main/scala/TestHarness.scala

@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 
-import scala.collection.mutable.{ArrayBuffer, HashMap}
+import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
@@ -31,10 +31,10 @@ trait HasHarnessSignalReferences {
 }
 
 class HarnessClockInstantiator {
-  private var _clockMap: HashMap[String, (Double, ClockBundle)] = HashMap.empty
+  private val _clockMap: LinkedHashMap[String, (Double, ClockBundle)] = LinkedHashMap.empty
 
   // request a clock bundle at a particular frequency
-  def getClockBundle(name: String, freqRequested: Double): ClockBundle = {
+  def requestClockBundle(name: String, freqRequested: Double): ClockBundle = {
     val clockBundle = Wire(new ClockBundle(ClockBundleParameters()))
     _clockMap(name) = (freqRequested, clockBundle)
     clockBundle
@@ -49,7 +49,7 @@ class HarnessClockInstantiator {
     val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks)
     pllConfig.emitSummaries()
 
-    val dividedClocks = HashMap[Int, Clock]()
+    val dividedClocks = LinkedHashMap[Int, Clock]()
     def instantiateDivider(div: Int): Clock = {
       val divider = Module(new ClockDividerN(div))
       divider.suggestName(s"ClockDivideBy${div}")
@@ -86,16 +86,15 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
   val harnessReset = Wire(Reset())
 
   val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
-  withClockAndReset(harnessClock, harnessReset) {
-    val dut = Module(lazyDut.module)
-  }
+  val dut = Module(lazyDut.module)
+
   io.success := false.B
 
   val freqMHz = lazyDut match {
     case d: HasReferenceClockFreq => d.refClockFreqMHz.getOrElse(p(DefaultClockFrequencyKey))
     case _ => p(DefaultClockFrequencyKey)
   }
-  val refClkBundle = p(HarnessClockInstantiatorKey).getClockBundle("buildtop_reference_clock", freqMHz * (1000 * 1000))
+  val refClkBundle = p(HarnessClockInstantiatorKey).requestClockBundle("buildtop_reference_clock", freqMHz * (1000 * 1000))
 
   harnessClock := refClkBundle.clock
   harnessReset := WireInit(refClkBundle.reset)

generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala

@@ -145,7 +145,3 @@ class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName
     }
   }
 }
-
-object DividerOnlyClockGenerator {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new DividerOnlyClockGenerator(valName.name))
-}