diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index a08abb6d..06f9af3b 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -53,15 +53,20 @@ class AbstractConfig extends Config( // By default, punch out IOs to the Harness new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus + new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus + new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus + new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus + new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address - new testchipip.WithSerialTLClientIdBits(4) ++ // support up to 1 << 4 simultaneous requests from serialTL port - new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance - new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM + new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams( // add a serial-tilelink interface + client = Some(testchipip.SerialTLClientParams(idBits = 4)), // serial-tilelink interface will master the FBUS, and support 4 idBits + width = 32 // serial-tilelink interface with 32 lanes + ))) ++ new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index cc61794c..95b0149b 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -23,7 +23,7 @@ class ChipLikeRocketConfig extends Config( // Set up I/O //================================== new testchipip.WithSerialTLWidth(4) ++ // 4bit wide Serialized TL interface to minimize IO - new testchipip.WithSerialTLBackingMemory ++ // Configure the off-chip memory accessible over serial-tl as backing memory + new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++ // Configure the off-chip memory accessible over serial-tl as backing memory new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 7ad7a1ac..790c6a0e 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -52,6 +52,9 @@ class MMIORocketConfig extends Config( new chipyard.config.AbstractConfig) class LBWIFRocketConfig extends Config( + new chipyard.config.WithOffchipBusFrequency(500) ++ + new testchipip.WithOffchipBusClient(MBUS) ++ + new testchipip.WithOffchipBus ++ new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index c45fb6f2..3a2c1b08 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -93,7 +93,6 @@ class MulticlockRocketConfig extends Config( new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between FBUS and SBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS new chipyard.config.AbstractConfig) class CustomIOChipTopRocketConfig extends Config( diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 2da9fbf2..c34be1bb 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -14,6 +14,8 @@ import freechips.rocketchip.tilelink.{HasTLBusParams} import chipyard._ import chipyard.clocking._ +import testchipip.{OffchipBusKey} + // The default RocketChip BaseSubsystem drives its diplomatic clock graph // with the implicit clocks of Subsystem. Don't do that, instead we extend // the diplomacy graph upwards into the ChipTop, where we connect it to @@ -103,6 +105,10 @@ class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => { case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) }) +class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) => { + case OffchipBusKey => up(OffchipBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong))) +}) + class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric)) class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing()) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 40f18d5d..51272e8a 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,7 +1,7 @@ package chipyard.config import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} +import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{DTSTimebase} // Replaces the L2 with a broadcast manager for maintaining coherence @@ -9,6 +9,10 @@ class WithBroadcastManager extends Config((site, here, up) => { case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) }) +class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => { + case BroadcastKey => params +}) + class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8) }) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index a1a1aeaa..a09bb06f 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -97,7 +97,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //========================= // Serialized TileLink //========================= - val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey)) + val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tls(0).getWrappedValue, "serial_tl", p(IOCellKey)) //========================= // JTAG/Debug diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 5b3168b3..5f6c69f1 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -39,8 +39,8 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1) // Serialized TL - val sVal = p(SerialTLKey).get - val serialTLManagerParams = sVal.serialTLManagerParams.get + val sVal = p(SerialTLKey)(0) + val serialTLManagerParams = sVal.manager.get require(serialTLManagerParams.isMemoryDevice) withClockAndReset(clock, reset) { @@ -49,10 +49,11 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { dut.serial_tl_pad.clock := clock } val harnessRAM = TSIHarness.connectRAM( - lazyDut.system.serdesser.get, + p(SerialTLKey)(0), + lazyDut.system.serdessers(0), serial_bits, reset) - io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset) + io.success := SimTSI.connect(harnessRAM.module.io.tsi, clock, reset) } diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index 8530bb33..94321506 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -215,13 +215,13 @@ class WithSimTSIOverSerialTL extends HarnessBinder({ if (DataMirror.directionOf(port.io.clock) == Direction.Input) { port.io.clock := th.harnessBinderClock } - val ram = LazyModule(new SerialRAM(port.serdesser)(port.serdesser.p)) + val ram = LazyModule(new SerialRAM(port.serdesser, port.params)(port.serdesser.p)) Module(ram.module) ram.module.io.ser <> port.io.bits val tsi = Module(new SimTSI) tsi.io.clock := th.harnessBinderClock tsi.io.reset := th.harnessBinderReset - tsi.io.tsi <> ram.module.io.tsi + tsi.io.tsi <> ram.module.io.tsi.get val exit = tsi.io.exit val success = exit === 1.U val error = exit >= 2.U diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 773f3d39..6c1cf8d2 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -342,10 +342,10 @@ class WithDebugIOCells extends OverrideLazyIOBinder({ class WithSerialTLIOCells extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { - val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) => + val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] - val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true) - (SerialTLPort(port, sys.p(SerialTLKey).get, system.serdesser.get, id), cells) + val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, s"serial_tl_$id", sys.p(IOCellKey), abstractResetAsAsync = true) + (SerialTLPort(port, sys.p(SerialTLKey)(id), system.serdessers(id), id), cells) }).unzip (ports.toSeq, cells.flatten.toSeq) } @@ -353,11 +353,11 @@ class WithSerialTLIOCells extends OverrideIOBinder({ class WithSerialTLPunchthrough extends OverrideIOBinder({ (system: CanHavePeripheryTLSerial) => { - val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) => + val (ports, cells) = system.serial_tls.zipWithIndex.map({ case (s, id) => val sys = system.asInstanceOf[BaseSubsystem] val port = IO(s.getWrappedValue.cloneType) port <> s.getWrappedValue - (SerialTLPort(port, sys.p(SerialTLKey).get, system.serdesser.get, id), Nil) + (SerialTLPort(port, sys.p(SerialTLKey)(id), system.serdessers(id), id), Nil) }).unzip (ports.toSeq, cells.flatten.toSeq) } diff --git a/generators/testchipip b/generators/testchipip index 6436959d..e1e1ee02 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6436959d997d0bb578790d95078648b478ca049b +Subproject commit e1e1ee02884f457f62785c41af23406a6cf7738a