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Merge pull request #1657 from ucb-bar/artygpio

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Add Bringup on Arty100T config, using PMOD-gpio for ser-tl
This commit is contained in:
Jerry Zhao
2023-11-19 13:45:18 -08:00
committed by GitHub
parent b84841704a 9dc0c8fe75
commit 6445233d8d
3 changed files with 65 additions and 25 deletions
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4
generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
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@@ -13,6 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}
import chipyard._
import chipyard.clocking._
import testchipip.{OffchipBusKey}
// The default RocketChip BaseSubsystem drives its diplomatic clock graph
// with the implicit clocks of Subsystem. Don't do that, instead we extend
@@ -103,6 +104,9 @@ class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) =>
class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})
class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
case OffchipBusKey => up(OffchipBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})
class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())