re-added macro placement

vlsi/example-designs/sky130-openroad.yml

@@ -5,3 +5,86 @@
 vlsi.inputs.clocks: [
   {name: "clock_clock", period: "30ns", uncertainty: "1ns"}
 ]
+
+# Placement Constraints
+vlsi.inputs.placement_constraints:
+  - path: "ChipTop"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 4000
+    height: 2500
+    margins:
+      left: 10
+      right: 10
+      top: 10
+      bottom: 10
+
+ # Place data cache SRAM instances
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 100
+    orientation: r0
+
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
+    type: hardmacro
+    x: 50
+    y: 700
+    orientation: r0
+
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
+    type: hardmacro
+    x: 50
+    y: 1300
+    orientation: r0
+
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
+    type: hardmacro
+    x: 50
+    y: 1900
+    orientation: r0
+
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
+    type: hardmacro
+    x: 1000
+    y: 1900
+    orientation: r0
+
+    
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
+    type: hardmacro
+    x: 1000 
+    y: 1300
+    orientation: r0
+    
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
+    type: hardmacro
+    x: 1000 
+    y: 700
+    orientation: r0
+
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
+    type: hardmacro
+    x: 1000 
+    y: 100
+    orientation: r0
+
+  # Place instruction cache SRAM instances
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
+    type: hardmacro
+    x: 3250
+    y: 100
+    orientation: r0
+
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
+    type: hardmacro
+    x: 3250
+    y: 700
+    orientation: r0
+
+  - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
+    type: hardmacro
+    x: 3450
+    y: 1300
+    orientation: r0

vlsi/example-designs/sky130-rocket.yml

@@ -3,7 +3,7 @@
 # Specify clock signals
 # Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
 vlsi.inputs.clocks: [
-  {name: "clock", period: "10ns", uncertainty: "1ns"}
+  {name: "clock", period: "5ns", uncertainty: "1ns"}
 ]
 
 # Placement Constraints