From 7de4c478c33458dc3f195e377543ce6bab9ba5b8 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 18 Feb 2020 14:56:17 -0800 Subject: [PATCH 1/3] Update to chisel 3.2.x --- build.sbt | 5 ++ .../transforms/.clkgen/ClkAnnotations.scala | 79 +++++++++---------- .../transforms/.pads/AddIOPadsTransform.scala | 8 +- .../transforms/.pads/AnnotateSupplyPads.scala | 14 ++-- .../transforms/.pads/ChiselTopModule.scala | 39 ++++----- .../scala/transforms/.pads/CreatePadBBs.scala | 18 ++--- .../transforms/.pads/FoundryPadsYaml.scala | 24 +++--- .../transforms/.pads/PadAnnotations.scala | 50 ++++++------ .../transforms/.pads/PadDescriptors.scala | 9 +-- 9 files changed, 124 insertions(+), 122 deletions(-) diff --git a/build.sbt b/build.sbt index d254ca24..9ec44bf7 100644 --- a/build.sbt +++ b/build.sbt @@ -39,6 +39,11 @@ lazy val macros = (project in file("macros")) lazy val tapeout = (project in file("tapeout")) .settings(commonSettings) + .settings(Seq( + libraryDependencies ++= Seq( + "io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0" + ) + )) .settings(scalacOptions in Test ++= Seq("-language:reflectiveCalls")) lazy val root = (project in file(".")).aggregate(macros, tapeout) diff --git a/tapeout/src/main/scala/transforms/.clkgen/ClkAnnotations.scala b/tapeout/src/main/scala/transforms/.clkgen/ClkAnnotations.scala index 832cfbb1..3a2f9ba3 100644 --- a/tapeout/src/main/scala/transforms/.clkgen/ClkAnnotations.scala +++ b/tapeout/src/main/scala/transforms/.clkgen/ClkAnnotations.scala @@ -42,8 +42,8 @@ case object ClkGen extends ClkModType { def serialize: String = "gen" } -// Unlike typical SDC, starts at 0. -// Otherwise, see pg. 63 of "Constraining Designs for Synthesis and Timing Analysis" +// Unlike typical SDC, starts at 0. +// Otherwise, see pg. 63 of "Constraining Designs for Synthesis and Timing Analysis" // by S. Gangadharan // original clk: |-----|_____|-----|_____| // edges: 0 1 2 3 4 @@ -51,9 +51,9 @@ case object ClkGen extends ClkModType { // ---> |-----------|___________| // sources = source id's case class GeneratedClk( - id: String, - sources: Seq[String] = Seq(), - referenceEdges: Seq[Int] = Seq(), + id: String, + sources: Seq[String] = Seq(), + referenceEdges: Seq[Int] = Seq(), period: Option[Double] = None) { require(referenceEdges.sorted == referenceEdges, "Edges must be in order for generated clk") if (referenceEdges.nonEmpty) require(referenceEdges.length % 2 == 1, "# of reference edges must be odd!") @@ -64,13 +64,13 @@ case class ClkModAnnotation(tpe: String, generatedClks: Seq[GeneratedClk]) { def modType: ClkModType = HasClkAnnotation.modType(tpe) modType match { - case ClkDiv => + case ClkDiv => generatedClks foreach { c => require(c.referenceEdges.nonEmpty, "Reference edges must be defined for clk divider!") require(c.sources.length == 1, "Clk divider output can only have 1 source") require(c.period.isEmpty, "No period should be specified for clk divider output") } - case ClkMux => + case ClkMux => generatedClks foreach { c => require(c.referenceEdges.isEmpty, "Reference edges must not be defined for clk mux!") require(c.period.isEmpty, "No period should be specified for clk mux output") @@ -92,22 +92,24 @@ abstract class FirrtlClkTransformAnnotation { } // Firrtl version -case class TargetClkModAnnoF(target: ModuleName, anno: ClkModAnnotation) extends FirrtlClkTransformAnnotation { +case class TargetClkModAnnoF(target: ModuleName, anno: ClkModAnnotation) extends FirrtlClkTransformAnnotation with SingleTargetAnnotation[ModuleName] { + def duplicate(n: ModuleName): TargetClkModAnnoF = this.copy(target = n) def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize) def targetName = target.name def modType = anno.modType def generatedClks = anno.generatedClks - def getAllClkPorts = anno.generatedClks.map(x => + def getAllClkPorts = anno.generatedClks.map(x => List(List(x.id), x.sources).flatten).flatten.distinct.map(Seq(targetName, _).mkString(".")) } // Chisel version -case class TargetClkModAnnoC(target: Module, anno: ClkModAnnotation) { - def getAnno = ChiselAnnotation(target, classOf[ClkSrcTransform], anno.serialize) +case class TargetClkModAnnoC(target: Module, anno: ClkModAnnotation) extends ChiselAnnotation { + def toFirrtl = TargetClkModAnnoF(target.toNamed, anno) } // Firrtl version -case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) extends FirrtlClkTransformAnnotation { +case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) extends FirrtlClkTransformAnnotation with SingleTargetAnnotation[ComponentName] { + def duplicate(n: ComponentName): TargetClkPortAnnoF = this.copy(target = n) def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize) def targetName = Seq(target.module.name, target.name).mkString(".") def modId = Seq(target.module.name, anno.id).mkString(".") @@ -115,8 +117,8 @@ case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) ex } // Chisel version -case class TargetClkPortAnnoC(target: Element, anno: ClkPortAnnotation) { - def getAnno = ChiselAnnotation(target, classOf[ClkSrcTransform], anno.serialize) +case class TargetClkPortAnnoC(target: Element, anno: ClkPortAnnotation) extends ChiselAnnotation { + def toFirrtl = TargetClkPortAnnoF(target.toNamed, anno) } object HasClkAnnotation { @@ -132,31 +134,31 @@ object HasClkAnnotation { def unapply(a: Annotation): Option[FirrtlClkTransformAnnotation] = a match { case Annotation(f, t, s) if t == classOf[ClkSrcTransform] => f match { - case m: ModuleName => + case m: ModuleName => Some(TargetClkModAnnoF(m, s.parseYaml.convertTo[ClkModAnnotation])) case c: ComponentName => Some(TargetClkPortAnnoF(c, s.parseYaml.convertTo[ClkPortAnnotation])) - case _ => throw new Exception("Clk source annotation only valid on module or component!") + case _ => throw new Exception("Clk source annotation only valid on module or component!") } case _ => None } def apply(annos: Seq[Annotation]): Option[(Seq[TargetClkModAnnoF],Seq[TargetClkPortAnnoF])] = { // Get all clk-related annotations - val clkAnnos = annos.map(x => unapply(x)).flatten + val clkAnnos = annos.map(x => unapply(x)).flatten val targets = clkAnnos.map(x => x.targetName) require(targets.distinct.length == targets.length, "Only 1 clk related annotation is allowed per component/module") if (clkAnnos.length == 0) None else { - val componentAnnos = clkAnnos.filter { + val componentAnnos = clkAnnos.filter { case TargetClkPortAnnoF(ComponentName(_, ModuleName(_, _)), _) => true case _ => false }.map(x => x.asInstanceOf[TargetClkPortAnnoF]) val associatedMods = componentAnnos.map(x => x.target.module.name) - val moduleAnnos = clkAnnos.filter { - case TargetClkModAnnoF(ModuleName(m, _), _) => + val moduleAnnos = clkAnnos.filter { + case TargetClkModAnnoF(ModuleName(m, _), _) => require(associatedMods contains m, "Clk modules should always have clk port annotations!") - true + true case _ => false }.map(x => x.asInstanceOf[TargetClkModAnnoF]) Some((moduleAnnos, componentAnnos)) @@ -170,29 +172,26 @@ trait IsClkModule { self: chisel3.Module => - private def doNotDedup(module: Module): Unit = { - annotate(ChiselAnnotation(module, classOf[DedupModules], "nodedup!")) - } doNotDedup(this) private def extractElementNames(signal: Data): Seq[String] = { val names = signal match { - case elt: Record => + case elt: Record => elt.elements.map { case (key, value) => extractElementNames(value).map(x => key + "_" + x) }.toSeq.flatten - case elt: Vec[_] => + case elt: Vec[_] => elt.zipWithIndex.map { case (elt, i) => extractElementNames(elt).map(x => i + "_" + x) }.toSeq.flatten case elt: Element => Seq("") case elt => throw new Exception(s"Cannot extractElementNames for type ${elt.getClass}") } - names.map(s => s.stripSuffix("_")) + names.map(s => s.stripSuffix("_")) } // TODO: Replace! def extractElements(signal: Data): Seq[Element] = { signal match { - case elt: Record => + case elt: Record => elt.elements.map { case (key, value) => extractElements(value) }.toSeq.flatten - case elt: Vec[_] => + case elt: Vec[_] => elt.map { elt => extractElements(elt) }.toSeq.flatten case elt: Element => Seq(elt) case elt => throw new Exception(s"Cannot extractElements for type ${elt.getClass}") @@ -200,7 +199,7 @@ trait IsClkModule { } def getIOName(signal: Element): String = { - val possibleNames = extractElements(io).zip(extractElementNames(io)).map { + val possibleNames = extractElements(io).zip(extractElementNames(io)).map { case (sig, name) if sig == signal => Some(name) case _ => None }.flatten @@ -208,11 +207,11 @@ trait IsClkModule { else throw new Exception("You can only get the name of an io port!") } - def annotateDerivedClks(tpe: ClkModType, generatedClks: Seq[GeneratedClk]): Unit = + def annotateDerivedClks(tpe: ClkModType, generatedClks: Seq[GeneratedClk]): Unit = annotateDerivedClks(ClkModAnnotation(tpe.serialize, generatedClks)) def annotateDerivedClks(anno: ClkModAnnotation): Unit = annotateDerivedClks(this, anno) - def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit = - annotate(TargetClkModAnnoC(m, anno).getAnno) + def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit = + annotate(TargetClkModAnnoC(m, anno)) def annotateClkPort(p: Element): Unit = annotateClkPort(p, None, "") def annotateClkPort(p: Element, sink: Sink): Unit = annotateClkPort(p, Some(sink), "") @@ -221,7 +220,7 @@ trait IsClkModule { def annotateClkPort(p: Element, sink: Option[Sink], id: String): Unit = { // If no id is specified, it'll try to figure out a name, assuming p is an io port val newId = id match { - case "" => + case "" => getIOName(p) case _ => id } @@ -229,12 +228,12 @@ trait IsClkModule { } def annotateClkPort(p: Element, anno: ClkPortAnnotation): Unit = { - p.dir match { - case chisel3.core.Direction.Input => + DataMirror.directionOf(p) match { + case chisel3.core.ActualDirection.Input => require(anno.tag.nonEmpty, "Module inputs must be clk sinks") - require(anno.tag.get.src.isEmpty, + require(anno.tag.get.src.isEmpty, "Clock module (not top) input clks should not have clk period, etc. specified") - case chisel3.core.Direction.Output => + case chisel3.core.ActualDirection.Output => require(anno.tag.isEmpty, "Module outputs must not be clk sinks (they're sources!)") case _ => throw new Exception("Clk port direction must be specified!") @@ -243,6 +242,6 @@ trait IsClkModule { case _: chisel3.core.Clock => case _ => throw new Exception("Clock port must be of type Clock") } - annotate(TargetClkPortAnnoC(p, anno).getAnno) + annotate(TargetClkPortAnnoC(p, anno)) } -} \ No newline at end of file +} diff --git a/tapeout/src/main/scala/transforms/.pads/AddIOPadsTransform.scala b/tapeout/src/main/scala/transforms/.pads/AddIOPadsTransform.scala index f9501f8f..d427d0d9 100644 --- a/tapeout/src/main/scala/transforms/.pads/AddIOPadsTransform.scala +++ b/tapeout/src/main/scala/transforms/.pads/AddIOPadsTransform.scala @@ -52,12 +52,12 @@ class AddIOPadsTransform extends Transform with SeqTransformBased { ) // Expects BlackBox helper to be run after to inline pad Verilog! val ret = runTransforms(state) - val currentAnnos = ret.annotations.getOrElse(AnnotationMap(Seq.empty)).annotations - val newAnnoMap = AnnotationMap(currentAnnos ++ bbAnnotations) - val newState = CircuitState(ret.circuit, outputForm, Some(newAnnoMap), ret.renames) + val currentAnnos = ret.annotations + val newAnnoMap = AnnotationSeq(currentAnnos ++ bbAnnotations) + val newState = CircuitState(ret.circuit, outputForm, newAnnoMap, ret.renames) // TODO: *.f file is overwritten on subsequent executions, but it doesn't seem to be used anywhere? (new firrtl.transforms.BlackBoxSourceHelper).execute(newState) } } -} \ No newline at end of file +} diff --git a/tapeout/src/main/scala/transforms/.pads/AnnotateSupplyPads.scala b/tapeout/src/main/scala/transforms/.pads/AnnotateSupplyPads.scala index 27b93b46..cda00791 100644 --- a/tapeout/src/main/scala/transforms/.pads/AnnotateSupplyPads.scala +++ b/tapeout/src/main/scala/transforms/.pads/AnnotateSupplyPads.scala @@ -22,13 +22,13 @@ case class TopSupplyPad( require(pad.padType == SupplyPad) def padOrientation = padSide.orientation - def getPadName = pad.getName(NoDirection, padOrientation) + def getPadName = pad.getName(Output/*Should be None*/, padOrientation) def firrtlBBName = getPadName private def instNamePrefix = Seq(firrtlBBName, padSide.serialize).mkString("_") def instNames = (0 until num).map(i => Seq(instNamePrefix, i.toString).mkString("_")) def createPadInline(): String = { - def getPadVerilog(): String = pad.getVerilog(NoDirection, padOrientation) + def getPadVerilog(): String = pad.getVerilog(Output/*Should be None*/, padOrientation) s"""inline |${getPadName}.v |${getPadVerilog}""".stripMargin @@ -37,14 +37,14 @@ case class TopSupplyPad( object AnnotateSupplyPads { def apply( - pads: Seq[FoundryPad], + pads: Seq[FoundryPad], supplyAnnos: Seq[SupplyAnnotation] ): Seq[TopSupplyPad] = { - supplyAnnos.map( a => + supplyAnnos.map( a => pads.find(_.name == a.padName) match { - case None => + case None => throw new Exception(s"Supply pad ${a.padName} not found in Yaml file!") - case Some(x) => + case Some(x) => Seq( TopSupplyPad(x, Left, a.leftSide), TopSupplyPad(x, Right, a.rightSide), @@ -53,4 +53,4 @@ object AnnotateSupplyPads { } ).flatten.filter(_.num > 0) } -} \ No newline at end of file +} diff --git a/tapeout/src/main/scala/transforms/.pads/ChiselTopModule.scala b/tapeout/src/main/scala/transforms/.pads/ChiselTopModule.scala index 8f891e62..36979ce5 100644 --- a/tapeout/src/main/scala/transforms/.pads/ChiselTopModule.scala +++ b/tapeout/src/main/scala/transforms/.pads/ChiselTopModule.scala @@ -8,8 +8,8 @@ import firrtl.transforms.DedupModules // TODO: Move out of pads // NOTE: You can't really annotate outside of the module itself UNLESS you break up the compile step in 2 i.e. -// annotate post-Chisel but pre-Firrtl (unfortunate non-generator friendly downside). -// It's recommended to have a Tapeout specific TopModule wrapper. +// annotate post-Chisel but pre-Firrtl (unfortunate non-generator friendly downside). +// It's recommended to have a Tapeout specific TopModule wrapper. // LIMITATION: All signals of a bus must be on the same chip side // Chisel-y annotations @@ -19,14 +19,17 @@ abstract class TopModule( coreWidth: Int = 0, coreHeight: Int = 0, usePads: Boolean = true, - override_clock: Option[Clock] = None, - override_reset: Option[Bool] = None) extends Module(override_clock, override_reset) with IsClkModule { + override_clock: Option[Clock] = None, + override_reset: Option[Bool] = None) extends Module with IsClkModule { + + override_clock.foreach(clock := _) + override_reset.foreach(reset := _) override def annotateClkPort(p: Element, anno: ClkPortAnnotation): Unit = { - p.dir match { - case chisel3.core.Direction.Input => + DataMirror.directionOf(p) match { + case chisel3.core.ActualDirection.Input => require(anno.tag.nonEmpty, "Top Module input clks must be clk sinks") - require(anno.tag.get.src.nonEmpty, + require(anno.tag.get.src.nonEmpty, "Top module input clks must have clk period, etc. specified") case _ => throw new Exception("Clk port direction must be specified!") @@ -35,10 +38,10 @@ abstract class TopModule( case _: chisel3.core.Clock => case _ => throw new Exception("Clock port must be of type Clock") } - annotate(TargetClkPortAnnoC(p, anno).getAnno) + annotate(TargetClkPortAnnoC(p, anno)) } - override def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit = + override def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit = throw new Exception("Top module cannot be pure clock module!") // Annotate module as top module (that requires pad transform) @@ -52,25 +55,25 @@ abstract class TopModule( coreHeight = coreHeight, supplyAnnos = supplyAnnos ) - annotate(TargetModulePadAnnoC(this, modulePadAnnotation).getAnno) + annotate(TargetModulePadAnnoC(this, modulePadAnnotation)) } - + // Annotate IO with side + pad name def annotatePad(sig: Element, side: PadSide = defaultPadSide, name: String = ""): Unit = if (usePads) { val anno = IOPadAnnotation(side.serialize, name) - annotate(TargetIOPadAnnoC(sig, anno).getAnno) + annotate(TargetIOPadAnnoC(sig, anno)) } def annotatePad(sig: Aggregate, name: String): Unit = annotatePad(sig, side = defaultPadSide, name) def annotatePad(sig: Aggregate, side: PadSide): Unit = annotatePad(sig, side, name = "") - def annotatePad(sig: Aggregate, side: PadSide, name: String): Unit = + def annotatePad(sig: Aggregate, side: PadSide, name: String): Unit = extractElements(sig) foreach { x => annotatePad(x, side, name) } - // There may be cases where pads were inserted elsewhere. If that's the case, allow certain IO to - // not have pads auto added. Note that annotatePad and noPad are mutually exclusive! - def noPad(sig: Element): Unit = if (usePads) annotate(TargetIOPadAnnoC(sig, NoIOPadAnnotation()).getAnno) + // There may be cases where pads were inserted elsewhere. If that's the case, allow certain IO to + // not have pads auto added. Note that annotatePad and noPad are mutually exclusive! + def noPad(sig: Element): Unit = if (usePads) annotate(TargetIOPadAnnoC(sig, NoIOPadAnnotation())) def noPad(sig: Aggregate): Unit = extractElements(sig) foreach { x => noPad(x) } - // Since this is a super class, this should be the first thing that gets run + // Since this is a super class, this should be the first thing that gets run // (at least when the module is actually at the top -- currently no guarantees otherwise :( firrtl limitation) createPads() -} \ No newline at end of file +} diff --git a/tapeout/src/main/scala/transforms/.pads/CreatePadBBs.scala b/tapeout/src/main/scala/transforms/.pads/CreatePadBBs.scala index 1a7f2aa9..5b35fbe4 100644 --- a/tapeout/src/main/scala/transforms/.pads/CreatePadBBs.scala +++ b/tapeout/src/main/scala/transforms/.pads/CreatePadBBs.scala @@ -40,7 +40,7 @@ object CreatePadBBs { } def checkLegalPadName(namespace: Namespace, usedPads: Seq[UsedPadInfo]): Unit = { - usedPads foreach { x => + usedPads foreach { x => if (namespace contains x.padName) throw new Exception(s"Pad name ${x.padName} already used!") if (namespace contains x.padArrayName) @@ -61,21 +61,21 @@ object CreatePadBBs { // Note that we need to check for Firrtl name uniqueness here! (due to parameterization) val uniqueExtMods = scala.collection.mutable.ArrayBuffer[UsedPadInfo]() - usedPads foreach { x => + usedPads foreach { x => if (uniqueExtMods.find(_.firrtlBBName == x.firrtlBBName).isEmpty) uniqueExtMods += x } - // Collecting unique parameterized black boxes + // Collecting unique parameterized black boxes // (for io, they're wrapped pads; for supply, they're pad modules directly) val uniqueParameterizedBBs = scala.collection.mutable.ArrayBuffer[UsedPadInfo]() - uniqueExtMods foreach { x => + uniqueExtMods foreach { x => if (uniqueParameterizedBBs.find(_.padArrayName == x.padArrayName).isEmpty) uniqueParameterizedBBs += x } - // Note: Firrtl is silly and doesn't implement true parameterization -- each module with - // parameterization that potentially affects # of IO needs to be uniquely identified + // Note: Firrtl is silly and doesn't implement true parameterization -- each module with + // parameterization that potentially affects # of IO needs to be uniquely identified // (but only in Firrtl) val bbs = uniqueExtMods.map(x => { // Supply pads don't have ports @@ -100,10 +100,10 @@ object CreatePadBBs { // Add annotations to black boxes to inline Verilog from template // Again, note the weirdness in parameterization -- just need to hook to one matching Firrtl instance - val annos = uniqueParameterizedBBs.map(x => - BlackBoxSourceAnnotation(ModuleName(x.firrtlBBName, CircuitName(c.main)), x.padInline) + val annos = uniqueParameterizedBBs.map(x => + BlackBoxInlineAnno(ModuleName(x.firrtlBBName, CircuitName(c.main)), x.firrtlBBName, x.padInline) ).toSeq (c.copy(modules = c.modules ++ bbs), annos) } -} \ No newline at end of file +} diff --git a/tapeout/src/main/scala/transforms/.pads/FoundryPadsYaml.scala b/tapeout/src/main/scala/transforms/.pads/FoundryPadsYaml.scala index ff1b92f0..2d372a51 100644 --- a/tapeout/src/main/scala/transforms/.pads/FoundryPadsYaml.scala +++ b/tapeout/src/main/scala/transforms/.pads/FoundryPadsYaml.scala @@ -7,11 +7,11 @@ import firrtl.ir._ import barstools.tapeout.transforms._ case class FoundryPad( - tpe: String, - name: String, - width: Int, + tpe: String, + name: String, + width: Int, height: Int, - supplySetNum: Option[Int], + supplySetNum: Option[Int], verilog: String) { def padInstName = "PAD" @@ -23,16 +23,16 @@ case class FoundryPad( def getSupplySetNum = supplySetNum.getOrElse(1) val padType = tpe match { - case "digital" => + case "digital" => require(verilog.contains(DigitalPad.inName), "Digital pad template must contain input called 'in'") require(verilog.contains(DigitalPad.outName), "Digital pad template must contain output called 'out'") require(verilog.contains("{{#if isInput}}"), "Digital pad template must contain '{{#if isInput}}'") DigitalPad - case "analog" => + case "analog" => require(verilog.contains(AnalogPad.ioName), "Analog pad template must contain inout called 'io'") require(!verilog.contains("{{#if isInput}}"), "Analog pad template must not contain '{{#if isInput}}'") AnalogPad - case "supply" => + case "supply" => // Supply pads don't have IO require(!verilog.contains("{{#if isInput}}"), "Supply pad template must not contain '{{#if isInput}}'") require( @@ -57,8 +57,8 @@ case class FoundryPad( private val orient = if (isHorizontal) Horizontal.serialize else Vertical.serialize private val dir = padType match { - case AnalogPad => InOut.serialize - case SupplyPad => NoDirection.serialize + case AnalogPad => "inout" + case SupplyPad => "none" case DigitalPad => if (isInput) Input.serialize else Output.serialize } val name = { @@ -69,7 +69,7 @@ case class FoundryPad( } // Note: Analog + supply don't use direction - private def getTemplateParams(dir: Direction, orient: PadOrientation): TemplateParams = + private def getTemplateParams(dir: Direction, orient: PadOrientation): TemplateParams = TemplateParams(isInput = (dir == Input), isHorizontal = (orient == Horizontal)) def getVerilog(dir: Direction, orient: PadOrientation): String = { @@ -85,11 +85,11 @@ object FoundryPadsYaml extends DefaultYamlProtocol { implicit val _pad = yamlFormat6(FoundryPad) def parse(techDir: String): Seq[FoundryPad] = { val file = techDir + exampleResource - if(techDir != "" && !(new java.io.File(file)).exists()) + if(techDir != "" && !(new java.io.File(file)).exists()) throw new Exception("Technology directory must contain FoundryPads.yaml!") val out = (new YamlFileReader(exampleResource)).parse[FoundryPad](if (techDir == "") "" else file) val padNames = out.map(x => x.correctedName) require(padNames.distinct.length == padNames.length, "Pad names must be unique!") out } -} \ No newline at end of file +} diff --git a/tapeout/src/main/scala/transforms/.pads/PadAnnotations.scala b/tapeout/src/main/scala/transforms/.pads/PadAnnotations.scala index 66b7f184..ed870092 100644 --- a/tapeout/src/main/scala/transforms/.pads/PadAnnotations.scala +++ b/tapeout/src/main/scala/transforms/.pads/PadAnnotations.scala @@ -21,7 +21,7 @@ abstract class FirrtlPadTransformAnnotation { // IO Port can either be annotated with padName + padSide OR noPad (mutually exclusive) abstract class IOAnnotation { - def serialize: String + def serialize: String } case class IOPadAnnotation(padSide: String, padName: String) extends IOAnnotation { import PadAnnotationsYaml._ @@ -31,29 +31,30 @@ case class IOPadAnnotation(padSide: String, padName: String) extends IOAnnotatio case class NoIOPadAnnotation(noPad: String = "") extends IOAnnotation { import PadAnnotationsYaml._ def serialize: String = this.toYaml.prettyPrint - def field = "noPad:" + def field = "noPad:" } // Firrtl version -case class TargetIOPadAnnoF(target: ComponentName, anno: IOAnnotation) extends FirrtlPadTransformAnnotation { +case class TargetIOPadAnnoF(target: ComponentName, anno: IOAnnotation) extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ComponentName] { + def duplicate(n: ComponentName): TargetIOPadAnnoF = this.copy(target = n) def getAnno = Annotation(target, classOf[AddIOPadsTransform], anno.serialize) def targetName = target.name } // Chisel version -case class TargetIOPadAnnoC(target: Element, anno: IOAnnotation) { - def getAnno = ChiselAnnotation(target, classOf[AddIOPadsTransform], anno.serialize) +case class TargetIOPadAnnoC(target: Element, anno: IOAnnotation) extends ChiselAnnotation { + def toFirrtl = TargetIOPadAnnoF(target.toNamed, anno) } // A bunch of supply pads (designated by name, # on each chip side) can be associated with the top module case class SupplyAnnotation( - padName: String, - leftSide: Int = 0, - rightSide: Int = 0, - topSide: Int = 0, + padName: String, + leftSide: Int = 0, + rightSide: Int = 0, + topSide: Int = 0, bottomSide: Int = 0) // The chip top should have a default pad side, a pad template file, and supply annotations case class ModulePadAnnotation( - defaultPadSide: String = Top.serialize, - coreWidth: Int = 0, + defaultPadSide: String = Top.serialize, + coreWidth: Int = 0, coreHeight: Int = 0, supplyAnnos: Seq[SupplyAnnotation] = Seq.empty) { import PadAnnotationsYaml._ @@ -63,13 +64,14 @@ case class ModulePadAnnotation( def getDefaultPadSide: PadSide = HasPadAnnotation.getSide(defaultPadSide) } // Firrtl version -case class TargetModulePadAnnoF(target: ModuleName, anno: ModulePadAnnotation) extends FirrtlPadTransformAnnotation { - def getAnno = Annotation(target, classOf[AddIOPadsTransform], anno.serialize) +case class TargetModulePadAnnoF(target: ModuleName, anno: ModulePadAnnotation) extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ModuleName] { + def duplicate(n: ModuleName): TargetModulePadAnnoF = this.copy(target = n) + def getAnno = Annotation(target, classOf[AddIOPadsTransform], anno.serialize) def targetName = target.name } // Chisel version -case class TargetModulePadAnnoC(target: Module, anno: ModulePadAnnotation) { - def getAnno = ChiselAnnotation(target, classOf[AddIOPadsTransform], anno.serialize) +case class TargetModulePadAnnoC(target: Module, anno: ModulePadAnnotation) extends ChiselAnnotation { + def toFirrtl = TargetModulePadAnnoF(target.toNamed, anno) } case class CollectedAnnos( @@ -95,9 +97,9 @@ object HasPadAnnotation { def unapply(a: Annotation): Option[FirrtlPadTransformAnnotation] = a match { case Annotation(f, t, s) if t == classOf[AddIOPadsTransform] => f match { - case m: ModuleName => + case m: ModuleName => Some(TargetModulePadAnnoF(m, s.parseYaml.convertTo[ModulePadAnnotation])) - case c: ComponentName if s.contains(NoIOPadAnnotation().field) => + case c: ComponentName if s.contains(NoIOPadAnnotation().field) => Some(TargetIOPadAnnoF(c, s.parseYaml.convertTo[NoIOPadAnnotation])) case c: ComponentName => Some(TargetIOPadAnnoF(c, s.parseYaml.convertTo[IOPadAnnotation])) @@ -108,26 +110,26 @@ object HasPadAnnotation { def apply(annos: Seq[Annotation]): Option[CollectedAnnos] = { // Get all pad-related annotations (config files, pad sides, pad names, etc.) - val padAnnos = annos.map(x => unapply(x)).flatten + val padAnnos = annos.map(x => unapply(x)).flatten val targets = padAnnos.map(x => x.targetName) require(targets.distinct.length == targets.length, "Only 1 pad related annotation is allowed per component/module") if (padAnnos.length == 0) None else { - val moduleAnnosTemp = padAnnos.filter { - case TargetModulePadAnnoF(_, _) => true + val moduleAnnosTemp = padAnnos.filter { + case TargetModulePadAnnoF(_, _) => true case _ => false } require(moduleAnnosTemp.length == 1, "Only 1 module may be designated 'Top'") val moduleAnnos = moduleAnnosTemp.head val topModName = moduleAnnos.targetName - val componentAnnos = padAnnos.filter { - case TargetIOPadAnnoF(ComponentName(_, ModuleName(n, _)), _) if n == topModName => + val componentAnnos = padAnnos.filter { + case TargetIOPadAnnoF(ComponentName(_, ModuleName(n, _)), _) if n == topModName => true - case TargetIOPadAnnoF(ComponentName(_, ModuleName(n, _)), _) if n != topModName => + case TargetIOPadAnnoF(ComponentName(_, ModuleName(n, _)), _) if n != topModName => throw new Exception("Pad related component annotations must all be in the same top module") case _ => false }.map(x => x.asInstanceOf[TargetIOPadAnnoF]) Some(CollectedAnnos(componentAnnos, moduleAnnos.asInstanceOf[TargetModulePadAnnoF])) } } -} \ No newline at end of file +} diff --git a/tapeout/src/main/scala/transforms/.pads/PadDescriptors.scala b/tapeout/src/main/scala/transforms/.pads/PadDescriptors.scala index 95a2cb1b..cb3420b1 100644 --- a/tapeout/src/main/scala/transforms/.pads/PadDescriptors.scala +++ b/tapeout/src/main/scala/transforms/.pads/PadDescriptors.scala @@ -28,13 +28,6 @@ case object NoPad extends PadType { def serialize: String = "none" } -case object InOut extends Direction { - def serialize: String = "inout" -} -case object NoDirection extends Direction { - def serialize: String = "none" -} - abstract class PadSide extends FirrtlNode { def orientation: PadOrientation } @@ -53,4 +46,4 @@ case object Top extends PadSide { case object Bottom extends PadSide { def serialize: String = "bottom" def orientation: PadOrientation = Vertical -} \ No newline at end of file +} From db0efd38fc8c842d994c8dcce5230e83ac7ba829 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 19 Feb 2020 17:23:10 -0800 Subject: [PATCH 2/3] Fix CI tests --- macros/src/test/scala/CostFunction.scala | 8 +- macros/src/test/scala/MultiPort.scala | 56 ++-- macros/src/test/scala/SimpleSplitDepth.scala | 12 +- macros/src/test/scala/SimpleSplitWidth.scala | 28 +- macros/src/test/scala/SpecificExamples.scala | 266 +++++++++--------- macros/src/test/scala/SynFlops.scala | 8 +- mdf | 2 +- .../main/scala/transforms/ResetInverter.scala | 3 +- .../scala/transforms/ResetInverterSpec.scala | 2 +- .../scala/transforms/retime/RetimeSpec.scala | 4 +- 10 files changed, 197 insertions(+), 192 deletions(-) diff --git a/macros/src/test/scala/CostFunction.scala b/macros/src/test/scala/CostFunction.scala index c82080b2..35936ed1 100644 --- a/macros/src/test/scala/CostFunction.scala +++ b/macros/src/test/scala/CostFunction.scala @@ -82,22 +82,22 @@ circuit target_memory : mem_0_0.addr <= addr node dout_0_0 = bits(mem_0_0.dout, 31, 0) mem_0_0.din <= bits(din, 31, 0) - mem_0_0.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_1.clk <= clk mem_0_1.addr <= addr node dout_0_1 = bits(mem_0_1.dout, 31, 0) mem_0_1.din <= bits(din, 63, 32) - mem_0_1.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_2.clk <= clk mem_0_2.addr <= addr node dout_0_2 = bits(mem_0_2.dout, 31, 0) mem_0_2.din <= bits(din, 95, 64) - mem_0_2.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_3.clk <= clk mem_0_3.addr <= addr node dout_0_3 = bits(mem_0_3.dout, 31, 0) mem_0_3.din <= bits(din, 127, 96) - mem_0_3.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node dout_0 = cat(dout_0_3, cat(dout_0_2, cat(dout_0_1, dout_0_0))) dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0")) diff --git a/macros/src/test/scala/MultiPort.scala b/macros/src/test/scala/MultiPort.scala index 470fee16..fdaae9f7 100644 --- a/macros/src/test/scala/MultiPort.scala +++ b/macros/src/test/scala/MultiPort.scala @@ -66,50 +66,50 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim node portA_dout_0_0 = bits(mem_0_0.portA_dout, 15, 0) mem_0_0.portA_din <= bits(portA_din, 15, 0) mem_0_0.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_0.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portA_clk <= portA_clk mem_0_1.portA_addr <= portA_addr node portA_dout_0_1 = bits(mem_0_1.portA_dout, 15, 0) mem_0_1.portA_din <= bits(portA_din, 31, 16) mem_0_1.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_1.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portA_clk <= portA_clk mem_0_2.portA_addr <= portA_addr node portA_dout_0_2 = bits(mem_0_2.portA_dout, 15, 0) mem_0_2.portA_din <= bits(portA_din, 47, 32) mem_0_2.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_2.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portA_clk <= portA_clk mem_0_3.portA_addr <= portA_addr node portA_dout_0_3 = bits(mem_0_3.portA_dout, 15, 0) mem_0_3.portA_din <= bits(portA_din, 63, 48) mem_0_3.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_3.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 3, 3)), UInt<1>("h1")) node portA_dout_0 = cat(portA_dout_0_3, cat(portA_dout_0_2, cat(portA_dout_0_1, portA_dout_0_0))) mem_0_0.portB_clk <= portB_clk mem_0_0.portB_addr <= portB_addr node portB_dout_0_0 = bits(mem_0_0.portB_dout, 15, 0) mem_0_0.portB_din <= bits(portB_din, 15, 0) mem_0_0.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_0.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portB_clk <= portB_clk mem_0_1.portB_addr <= portB_addr node portB_dout_0_1 = bits(mem_0_1.portB_dout, 15, 0) mem_0_1.portB_din <= bits(portB_din, 31, 16) mem_0_1.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_1.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portB_clk <= portB_clk mem_0_2.portB_addr <= portB_addr node portB_dout_0_2 = bits(mem_0_2.portB_dout, 15, 0) mem_0_2.portB_din <= bits(portB_din, 47, 32) mem_0_2.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_2.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portB_clk <= portB_clk mem_0_3.portB_addr <= portB_addr node portB_dout_0_3 = bits(mem_0_3.portB_dout, 15, 0) mem_0_3.portB_din <= bits(portB_din, 63, 48) mem_0_3.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_3.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1")) node portB_dout_0 = cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0))) portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0")) portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0")) @@ -185,19 +185,19 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS mem_0_0.portB_clk <= portB_clk mem_0_0.portB_addr <= portB_addr mem_0_0.portB_din <= bits(portB_din, 15, 0) - mem_0_0.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portB_clk <= portB_clk mem_0_1.portB_addr <= portB_addr mem_0_1.portB_din <= bits(portB_din, 31, 16) - mem_0_1.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portB_clk <= portB_clk mem_0_2.portB_addr <= portB_addr mem_0_2.portB_din <= bits(portB_din, 47, 32) - mem_0_2.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portB_clk <= portB_clk mem_0_3.portB_addr <= portB_addr mem_0_3.portB_din <= bits(portB_din, 63, 48) - mem_0_3.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1")) mem_0_0.portA_clk <= portA_clk mem_0_0.portA_addr <= portA_addr node portA_dout_0_0 = bits(mem_0_0.portA_dout, 15, 0) @@ -291,98 +291,98 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera node portA_dout_0_0 = bits(mem_0_0.portA_dout, 7, 0) mem_0_0.portA_din <= bits(portA_din, 7, 0) mem_0_0.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_0.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portA_clk <= portA_clk mem_0_1.portA_addr <= portA_addr node portA_dout_0_1 = bits(mem_0_1.portA_dout, 7, 0) mem_0_1.portA_din <= bits(portA_din, 15, 8) mem_0_1.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_1.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 0, 0)), UInt<1>("h1")) + mem_0_1.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 0, 0)), UInt<1>("h1")) mem_0_2.portA_clk <= portA_clk mem_0_2.portA_addr <= portA_addr node portA_dout_0_2 = bits(mem_0_2.portA_dout, 7, 0) mem_0_2.portA_din <= bits(portA_din, 23, 16) mem_0_2.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_2.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 1, 1)), UInt<1>("h1")) + mem_0_2.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 1, 1)), UInt<1>("h1")) mem_0_3.portA_clk <= portA_clk mem_0_3.portA_addr <= portA_addr node portA_dout_0_3 = bits(mem_0_3.portA_dout, 7, 0) mem_0_3.portA_din <= bits(portA_din, 31, 24) mem_0_3.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_3.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 1, 1)), UInt<1>("h1")) + mem_0_3.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 1, 1)), UInt<1>("h1")) mem_0_4.portA_clk <= portA_clk mem_0_4.portA_addr <= portA_addr node portA_dout_0_4 = bits(mem_0_4.portA_dout, 7, 0) mem_0_4.portA_din <= bits(portA_din, 39, 32) mem_0_4.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_4.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 2, 2)), UInt<1>("h1")) + mem_0_4.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 2, 2)), UInt<1>("h1")) mem_0_5.portA_clk <= portA_clk mem_0_5.portA_addr <= portA_addr node portA_dout_0_5 = bits(mem_0_5.portA_dout, 7, 0) mem_0_5.portA_din <= bits(portA_din, 47, 40) mem_0_5.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_5.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 2, 2)), UInt<1>("h1")) + mem_0_5.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 2, 2)), UInt<1>("h1")) mem_0_6.portA_clk <= portA_clk mem_0_6.portA_addr <= portA_addr node portA_dout_0_6 = bits(mem_0_6.portA_dout, 7, 0) mem_0_6.portA_din <= bits(portA_din, 55, 48) mem_0_6.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_6.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 3, 3)), UInt<1>("h1")) + mem_0_6.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 3, 3)), UInt<1>("h1")) mem_0_7.portA_clk <= portA_clk mem_0_7.portA_addr <= portA_addr node portA_dout_0_7 = bits(mem_0_7.portA_dout, 7, 0) mem_0_7.portA_din <= bits(portA_din, 63, 56) mem_0_7.portA_read_en <= and(portA_read_en, UInt<1>("h1")) - mem_0_7.portA_write_en <= and(and(portA_write_en, bits(portA_mask, 3, 3)), UInt<1>("h1")) + mem_0_7.portA_write_en <= and(and(and(portA_write_en, UInt<1>("h1")), bits(portA_mask, 3, 3)), UInt<1>("h1")) node portA_dout_0 = cat(portA_dout_0_7, cat(portA_dout_0_6, cat(portA_dout_0_5, cat(portA_dout_0_4, cat(portA_dout_0_3, cat(portA_dout_0_2, cat(portA_dout_0_1, portA_dout_0_0))))))) mem_0_0.portB_clk <= portB_clk mem_0_0.portB_addr <= portB_addr node portB_dout_0_0 = bits(mem_0_0.portB_dout, 7, 0) mem_0_0.portB_din <= bits(portB_din, 7, 0) mem_0_0.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_0.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 0, 0)), UInt<1>("h1")) + mem_0_0.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 0, 0)), UInt<1>("h1")) mem_0_1.portB_clk <= portB_clk mem_0_1.portB_addr <= portB_addr node portB_dout_0_1 = bits(mem_0_1.portB_dout, 7, 0) mem_0_1.portB_din <= bits(portB_din, 15, 8) mem_0_1.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_1.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 1, 1)), UInt<1>("h1")) + mem_0_1.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 1, 1)), UInt<1>("h1")) mem_0_2.portB_clk <= portB_clk mem_0_2.portB_addr <= portB_addr node portB_dout_0_2 = bits(mem_0_2.portB_dout, 7, 0) mem_0_2.portB_din <= bits(portB_din, 23, 16) mem_0_2.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_2.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 2, 2)), UInt<1>("h1")) + mem_0_2.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 2, 2)), UInt<1>("h1")) mem_0_3.portB_clk <= portB_clk mem_0_3.portB_addr <= portB_addr node portB_dout_0_3 = bits(mem_0_3.portB_dout, 7, 0) mem_0_3.portB_din <= bits(portB_din, 31, 24) mem_0_3.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_3.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 3, 3)), UInt<1>("h1")) + mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1")) mem_0_4.portB_clk <= portB_clk mem_0_4.portB_addr <= portB_addr node portB_dout_0_4 = bits(mem_0_4.portB_dout, 7, 0) mem_0_4.portB_din <= bits(portB_din, 39, 32) mem_0_4.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_4.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 4, 4)), UInt<1>("h1")) + mem_0_4.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 4, 4)), UInt<1>("h1")) mem_0_5.portB_clk <= portB_clk mem_0_5.portB_addr <= portB_addr node portB_dout_0_5 = bits(mem_0_5.portB_dout, 7, 0) mem_0_5.portB_din <= bits(portB_din, 47, 40) mem_0_5.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_5.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 5, 5)), UInt<1>("h1")) + mem_0_5.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 5, 5)), UInt<1>("h1")) mem_0_6.portB_clk <= portB_clk mem_0_6.portB_addr <= portB_addr node portB_dout_0_6 = bits(mem_0_6.portB_dout, 7, 0) mem_0_6.portB_din <= bits(portB_din, 55, 48) mem_0_6.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_6.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 6, 6)), UInt<1>("h1")) + mem_0_6.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 6, 6)), UInt<1>("h1")) mem_0_7.portB_clk <= portB_clk mem_0_7.portB_addr <= portB_addr node portB_dout_0_7 = bits(mem_0_7.portB_dout, 7, 0) mem_0_7.portB_din <= bits(portB_din, 63, 56) mem_0_7.portB_read_en <= and(portB_read_en, UInt<1>("h1")) - mem_0_7.portB_write_en <= and(and(portB_write_en, bits(portB_mask, 7, 7)), UInt<1>("h1")) + mem_0_7.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 7, 7)), UInt<1>("h1")) node portB_dout_0 = cat(portB_dout_0_7, cat(portB_dout_0_6, cat(portB_dout_0_5, cat(portB_dout_0_4, cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0))))))) portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0")) portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0")) diff --git a/macros/src/test/scala/SimpleSplitDepth.scala b/macros/src/test/scala/SimpleSplitDepth.scala index 18b4a930..8df8ec7e 100644 --- a/macros/src/test/scala/SimpleSplitDepth.scala +++ b/macros/src/test/scala/SimpleSplitDepth.scala @@ -31,6 +31,8 @@ s""" for (i <- 0 to depthInstances - 1) { val maskStatement = generateMaskStatement(0, i) val enableIdentifier = if (selectBits > 0) s"""eq(${memPortPrefix}_addr_sel, UInt<${selectBits}>("h${i.toHexString}"))""" else "UInt<1>(\"h1\")" + val chipEnable = s"""UInt<1>("h1")""" + val writeEnable = if (memMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, ${chipEnable})" else s"${memPortPrefix}_write_en" output.append( s""" inst mem_${i}_0 of ${lib_name} @@ -39,7 +41,7 @@ s""" node ${memPortPrefix}_dout_${i}_0 = bits(mem_${i}_0.${libPortPrefix}_dout, ${width - 1}, 0) mem_${i}_0.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${width - 1}, 0) ${maskStatement} - mem_${i}_0.${libPortPrefix}_write_en <= and(and(${memPortPrefix}_write_en, UInt<1>("h1")), ${enableIdentifier}) + mem_${i}_0.${libPortPrefix}_write_en <= and(and(${writeEnable}, UInt<1>("h1")), ${enableIdentifier}) node ${memPortPrefix}_dout_${i} = ${memPortPrefix}_dout_${i}_0 """ ) @@ -273,7 +275,7 @@ circuit target_memory : node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0) mem_0_0.lib_din <= bits(outer_din, 7, 0) - mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h0"))) + mem_0_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h0"))) node outer_dout_0 = outer_dout_0_0 inst mem_1_0 of awesome_lib_mem @@ -283,7 +285,7 @@ circuit target_memory : node outer_dout_1_0 = bits(mem_1_0.lib_dout, 7, 0) mem_1_0.lib_din <= bits(outer_din, 7, 0) - mem_1_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1"))) + mem_1_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1"))) node outer_dout_1 = outer_dout_1_0 outer_dout <= mux(eq(outer_addr_sel_reg, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel_reg, UInt<1>("h1")), outer_dout_1, UInt<1>("h0"))) extmodule awesome_lib_mem : @@ -362,7 +364,7 @@ circuit target_memory : mem_0_0.innerB_clk <= outerA_clk mem_0_0.innerB_addr <= outerA_addr mem_0_0.innerB_din <= bits(outerA_din, 7, 0) - mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) + mem_0_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) mem_0_0.innerA_clk <= outerB_clk mem_0_0.innerA_addr <= outerB_addr node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0) @@ -371,7 +373,7 @@ circuit target_memory : mem_1_0.innerB_clk <= outerA_clk mem_1_0.innerB_addr <= outerA_addr mem_1_0.innerB_din <= bits(outerA_din, 7, 0) - mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) + mem_1_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) mem_1_0.innerA_clk <= outerB_clk mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) diff --git a/macros/src/test/scala/SimpleSplitWidth.scala b/macros/src/test/scala/SimpleSplitWidth.scala index 3d26c18d..9cc10f9d 100644 --- a/macros/src/test/scala/SimpleSplitWidth.scala +++ b/macros/src/test/scala/SimpleSplitWidth.scala @@ -38,6 +38,8 @@ trait HasSimpleWidthTestGenerator extends HasSimpleTestGenerator { val outerMaskBit = myBaseBit / memMaskGran.get s"bits(outer_mask, ${outerMaskBit}, ${outerMaskBit})" } else """UInt<1>("h1")""" + val chipEnable = s"""UInt<1>("h1")""" + val writeEnableExpr = if (libMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, ${chipEnable})" else s"${memPortPrefix}_write_en" s""" mem_0_${i}.${libPortPrefix}_clk <= ${memPortPrefix}_clk @@ -45,7 +47,7 @@ s""" node ${memPortPrefix}_dout_0_${i} = bits(mem_0_${i}.${libPortPrefix}_dout, ${myMemWidth - 1}, 0) mem_0_${i}.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${myBaseBit + myMemWidth - 1}, ${myBaseBit}) ${maskStatement} - mem_0_${i}.${libPortPrefix}_write_en <= and(and(${memPortPrefix}_write_en, ${writeEnableBit}), UInt<1>("h1")) + mem_0_${i}.${libPortPrefix}_write_en <= and(and(${writeEnableExpr}, ${writeEnableBit}), UInt<1>("h1")) """ }).reduceLeft(_ + _) @@ -415,26 +417,26 @@ class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGen mem_0_0.lib_addr <= outer_addr node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0) mem_0_0.lib_din <= bits(outer_din, 7, 0) - mem_0_0.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_1.lib_clk <= outer_clk mem_0_1.lib_addr <= outer_addr node outer_dout_0_1 = bits(mem_0_1.lib_dout, 7, 0) mem_0_1.lib_din <= bits(outer_din, 15, 8) - mem_0_1.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_1.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_2.lib_clk <= outer_clk mem_0_2.lib_addr <= outer_addr node outer_dout_0_2 = bits(mem_0_2.lib_dout, 7, 0) mem_0_2.lib_din <= bits(outer_din, 23, 16) - mem_0_2.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_2.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_3.lib_clk <= outer_clk mem_0_3.lib_addr <= outer_addr node outer_dout_0_3 = bits(mem_0_3.lib_dout, 7, 0) mem_0_3.lib_din <= bits(outer_din, 31, 24) - mem_0_3.lib_read_en <= and(not(outer_write_en), UInt<1>("h1")) - mem_0_3.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))) outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) """ @@ -514,25 +516,25 @@ class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAM node outer_dout_0_0 = bits(mem_0_0.lib_dout, 7, 0) mem_0_0.lib_din <= bits(outer_din, 7, 0) mem_0_0.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_1.lib_clk <= outer_clk mem_0_1.lib_addr <= outer_addr node outer_dout_0_1 = bits(mem_0_1.lib_dout, 7, 0) mem_0_1.lib_din <= bits(outer_din, 15, 8) mem_0_1.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_1.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_1.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_2.lib_clk <= outer_clk mem_0_2.lib_addr <= outer_addr node outer_dout_0_2 = bits(mem_0_2.lib_dout, 7, 0) mem_0_2.lib_din <= bits(outer_din, 23, 16) mem_0_2.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_2.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_2.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_3.lib_clk <= outer_clk mem_0_3.lib_addr <= outer_addr node outer_dout_0_3 = bits(mem_0_3.lib_dout, 7, 0) mem_0_3.lib_din <= bits(outer_din, 31, 24) mem_0_3.lib_read_en <= and(outer_read_en, UInt<1>("h1")) - mem_0_3.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))) outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) """ diff --git a/macros/src/test/scala/SpecificExamples.scala b/macros/src/test/scala/SpecificExamples.scala index 7179d20f..56f4500f 100644 --- a/macros/src/test/scala/SpecificExamples.scala +++ b/macros/src/test/scala/SpecificExamples.scala @@ -59,34 +59,34 @@ class WriteEnableTest extends MacroCompilerSpec with HasSRAMGenerator { val output = """ - circuit cc_banks_0_ext : - module cc_banks_0_ext : - input RW0_addr : UInt<12> - input RW0_clk : Clock - input RW0_wdata : UInt<64> - output RW0_rdata : UInt<64> - input RW0_en : UInt<1> - input RW0_wmode : UInt<1> +circuit cc_banks_0_ext : + module cc_banks_0_ext : + input RW0_addr : UInt<12> + input RW0_clk : Clock + input RW0_wdata : UInt<64> + output RW0_rdata : UInt<64> + input RW0_en : UInt<1> + input RW0_wmode : UInt<1> - inst mem_0_0 of fake_mem - mem_0_0.clk <= RW0_clk - mem_0_0.addr <= RW0_addr - node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0) - mem_0_0.datain <= bits(RW0_wdata, 63, 0) - mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) - mem_0_0.wen <= and(and(and(RW0_wmode, RW0_en), UInt<1>("h1")), UInt<1>("h1")) - node RW0_rdata_0 = RW0_rdata_0_0 - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + inst mem_0_0 of fake_mem + mem_0_0.clk <= RW0_clk + mem_0_0.addr <= RW0_addr + node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0) + mem_0_0.datain <= bits(RW0_wdata, 63, 0) + mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) + mem_0_0.wen <= and(and(and(RW0_wmode, RW0_en), UInt<1>("h1")), UInt<1>("h1")) + node RW0_rdata_0 = RW0_rdata_0_0 + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) - extmodule fake_mem : - input addr : UInt<12> - input clk : Clock - input datain : UInt<64> - output dataout : UInt<64> - input ren : UInt<1> - input wen : UInt<1> + extmodule fake_mem : + input addr : UInt<12> + input clk : Clock + input datain : UInt<64> + output dataout : UInt<64> + input ren : UInt<1> + input wen : UInt<1> - defname = fake_mem + defname = fake_mem """ compileExecuteAndTest(mem, lib, v, output) @@ -148,14 +148,14 @@ circuit cc_dir_ext : mem_0_0.addr <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0) mem_0_0.datain <= bits(RW0_wdata, 63, 0) - mem_0_0.ren <= and(not(RW0_wmode), UInt<1>("h1")) + mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) mem_0_0.mport <= not(cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), bits(RW0_wmask, 0, 0))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) mem_0_0.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1")) mem_0_1.clk <= RW0_clk mem_0_1.addr <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.dataout, 63, 0) mem_0_1.datain <= bits(RW0_wdata, 127, 64) - mem_0_1.ren <= and(not(RW0_wmode), UInt<1>("h1")) + mem_0_1.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) mem_0_1.mport <= not(cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), bits(RW0_wmask, 4, 4))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) mem_0_1.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1")) node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0) @@ -379,53 +379,53 @@ circuit smem_0_ext : mem_0_0.CE1 <= W0_clk mem_0_0.A1 <= W0_addr mem_0_0.I1 <= bits(W0_data, 21, 0) - mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_1.CE1 <= W0_clk mem_0_1.A1 <= W0_addr mem_0_1.I1 <= bits(W0_data, 43, 22) - mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_2.CE1 <= W0_clk mem_0_2.A1 <= W0_addr mem_0_2.I1 <= bits(W0_data, 65, 44) - mem_0_2.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_2.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_2.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_2.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_3.CE1 <= W0_clk mem_0_3.A1 <= W0_addr mem_0_3.I1 <= bits(W0_data, 87, 66) - mem_0_3.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h0")))) + mem_0_3.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_3.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), eq(W0_addr_sel, UInt<1>("h0")))) mem_0_3.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h0")))) mem_0_0.CE2 <= R0_clk mem_0_0.A2 <= R0_addr node R0_data_0_0 = bits(mem_0_0.O2, 21, 0) mem_0_0.I2 is invalid - mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) mem_0_1.CE2 <= R0_clk mem_0_1.A2 <= R0_addr node R0_data_0_1 = bits(mem_0_1.O2, 21, 0) mem_0_1.I2 is invalid - mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) mem_0_2.CE2 <= R0_clk mem_0_2.A2 <= R0_addr node R0_data_0_2 = bits(mem_0_2.O2, 21, 0) mem_0_2.I2 is invalid - mem_0_2.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_2.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_2.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_2.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) mem_0_3.CE2 <= R0_clk mem_0_3.A2 <= R0_addr node R0_data_0_3 = bits(mem_0_3.O2, 21, 0) mem_0_3.I2 is invalid - mem_0_3.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h0")))) + mem_0_3.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h0")))) mem_0_3.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h0")))) node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0))) @@ -436,53 +436,53 @@ circuit smem_0_ext : mem_1_0.CE1 <= W0_clk mem_1_0.A1 <= W0_addr mem_1_0.I1 <= bits(W0_data, 21, 0) - mem_1_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_1.CE1 <= W0_clk mem_1_1.A1 <= W0_addr mem_1_1.I1 <= bits(W0_data, 43, 22) - mem_1_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 1, 1)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_2.CE1 <= W0_clk mem_1_2.A1 <= W0_addr mem_1_2.I1 <= bits(W0_data, 65, 44) - mem_1_2.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_2.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_2.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 2, 2)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_2.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_3.CE1 <= W0_clk mem_1_3.A1 <= W0_addr mem_1_3.I1 <= bits(W0_data, 87, 66) - mem_1_3.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<1>("h1")))) + mem_1_3.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_3.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 3, 3)), eq(W0_addr_sel, UInt<1>("h1")))) mem_1_3.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<1>("h1")))) mem_1_0.CE2 <= R0_clk mem_1_0.A2 <= R0_addr node R0_data_1_0 = bits(mem_1_0.O2, 21, 0) mem_1_0.I2 is invalid - mem_1_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) mem_1_1.CE2 <= R0_clk mem_1_1.A2 <= R0_addr node R0_data_1_1 = bits(mem_1_1.O2, 21, 0) mem_1_1.I2 is invalid - mem_1_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) mem_1_2.CE2 <= R0_clk mem_1_2.A2 <= R0_addr node R0_data_1_2 = bits(mem_1_2.O2, 21, 0) mem_1_2.I2 is invalid - mem_1_2.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_2.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_2.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_2.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) mem_1_3.CE2 <= R0_clk mem_1_3.A2 <= R0_addr node R0_data_1_3 = bits(mem_1_3.O2, 21, 0) mem_1_3.I2 is invalid - mem_1_3.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<1>("h1")))) + mem_1_3.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_3.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) node R0_data_1 = cat(R0_data_1_3, cat(R0_data_1_2, cat(R0_data_1_1, R0_data_1_0))) @@ -510,27 +510,27 @@ circuit smem_0_ext : mem_0_0.CE1 <= W0_clk mem_0_0.A1 <= W0_addr mem_0_0.I1 <= bits(W0_data, 31, 0) - mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h0")))) + mem_0_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h0")))) mem_0_1.CE1 <= W0_clk mem_0_1.A1 <= W0_addr mem_0_1.I1 <= bits(W0_data, 63, 32) - mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h0")))) + mem_0_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h0")))) mem_0_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h0")))) mem_0_0.CE2 <= R0_clk mem_0_0.A2 <= R0_addr node R0_data_0_0 = bits(mem_0_0.O2, 31, 0) mem_0_0.I2 is invalid - mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h0")))) + mem_0_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h0")))) mem_0_1.CE2 <= R0_clk mem_0_1.A2 <= R0_addr node R0_data_0_1 = bits(mem_0_1.O2, 31, 0) mem_0_1.I2 is invalid - mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h0")))) + mem_0_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h0")))) mem_0_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h0")))) node R0_data_0 = cat(R0_data_0_1, R0_data_0_0) @@ -539,27 +539,27 @@ circuit smem_0_ext : mem_1_0.CE1 <= W0_clk mem_1_0.A1 <= W0_addr mem_1_0.I1 <= bits(W0_data, 31, 0) - mem_1_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h1")))) + mem_1_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h1")))) mem_1_1.CE1 <= W0_clk mem_1_1.A1 <= W0_addr mem_1_1.I1 <= bits(W0_data, 63, 32) - mem_1_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h1")))) + mem_1_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h1")))) mem_1_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h1")))) mem_1_0.CE2 <= R0_clk mem_1_0.A2 <= R0_addr node R0_data_1_0 = bits(mem_1_0.O2, 31, 0) mem_1_0.I2 is invalid - mem_1_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h1")))) + mem_1_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h1")))) mem_1_1.CE2 <= R0_clk mem_1_1.A2 <= R0_addr node R0_data_1_1 = bits(mem_1_1.O2, 31, 0) mem_1_1.I2 is invalid - mem_1_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h1")))) + mem_1_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h1")))) mem_1_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h1")))) node R0_data_1 = cat(R0_data_1_1, R0_data_1_0) @@ -568,27 +568,27 @@ circuit smem_0_ext : mem_2_0.CE1 <= W0_clk mem_2_0.A1 <= W0_addr mem_2_0.I1 <= bits(W0_data, 31, 0) - mem_2_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h2")))) + mem_2_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h2")))) mem_2_1.CE1 <= W0_clk mem_2_1.A1 <= W0_addr mem_2_1.I1 <= bits(W0_data, 63, 32) - mem_2_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h2")))) + mem_2_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h2")))) mem_2_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h2")))) mem_2_0.CE2 <= R0_clk mem_2_0.A2 <= R0_addr node R0_data_2_0 = bits(mem_2_0.O2, 31, 0) mem_2_0.I2 is invalid - mem_2_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h2")))) + mem_2_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h2")))) mem_2_1.CE2 <= R0_clk mem_2_1.A2 <= R0_addr node R0_data_2_1 = bits(mem_2_1.O2, 31, 0) mem_2_1.I2 is invalid - mem_2_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h2")))) + mem_2_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h2")))) mem_2_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h2")))) node R0_data_2 = cat(R0_data_2_1, R0_data_2_0) @@ -597,27 +597,27 @@ circuit smem_0_ext : mem_3_0.CE1 <= W0_clk mem_3_0.A1 <= W0_addr mem_3_0.I1 <= bits(W0_data, 31, 0) - mem_3_0.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h3")))) + mem_3_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_0.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_0.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h3")))) mem_3_1.CE1 <= W0_clk mem_3_1.A1 <= W0_addr mem_3_1.I1 <= bits(W0_data, 63, 32) - mem_3_1.OEB1 <= not(and(not(UInt<1>("h1")), eq(W0_addr_sel, UInt<2>("h3")))) + mem_3_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_1.WEB1 <= not(and(and(UInt<1>("h1"), bits(W0_mask, 0, 0)), eq(W0_addr_sel, UInt<2>("h3")))) mem_3_1.CSB1 <= not(and(W0_en, eq(W0_addr_sel, UInt<2>("h3")))) mem_3_0.CE2 <= R0_clk mem_3_0.A2 <= R0_addr node R0_data_3_0 = bits(mem_3_0.O2, 31, 0) mem_3_0.I2 is invalid - mem_3_0.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h3")))) + mem_3_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_0.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h3")))) mem_3_1.CE2 <= R0_clk mem_3_1.A2 <= R0_addr node R0_data_3_1 = bits(mem_3_1.O2, 31, 0) mem_3_1.I2 is invalid - mem_3_1.OEB2 <= not(and(not(UInt<1>("h0")), eq(R0_addr_sel, UInt<2>("h3")))) + mem_3_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h3")))) node R0_data_3 = cat(R0_data_3_1, R0_data_3_0) @@ -659,28 +659,28 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 19, 0) mem_0_0.I <= bits(RW0_wdata, 19, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 19, 0) mem_0_1.I <= bits(RW0_wdata, 39, 20) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_2.CE <= RW0_clk mem_0_2.A <= RW0_addr node RW0_rdata_0_2 = bits(mem_0_2.O, 19, 0) mem_0_2.I <= bits(RW0_wdata, 59, 40) - mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_2.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))) mem_0_2.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_3.CE <= RW0_clk mem_0_3.A <= RW0_addr node RW0_rdata_0_3 = bits(mem_0_3.O, 19, 0) mem_0_3.I <= bits(RW0_wdata, 79, 60) - mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_3.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))) mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))) @@ -712,14 +712,14 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 31, 0) mem_0_0.I <= bits(RW0_wdata, 31, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 31, 0) mem_0_1.I <= bits(RW0_wdata, 63, 32) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0) @@ -752,27 +752,27 @@ circuit smem_0_ext : mem_0_0.CE1 <= W0_clk mem_0_0.A1 <= W0_addr mem_0_0.I1 <= bits(W0_data, 21, 0) - mem_0_0.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1"))) + mem_0_0.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), UInt<1>("h1"))) mem_0_0.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_0.CSB1 <= not(and(W0_en, UInt<1>("h1"))) mem_0_1.CE1 <= W0_clk mem_0_1.A1 <= W0_addr mem_0_1.I1 <= bits(W0_data, 39, 22) - mem_0_1.OEB1 <= not(and(not(UInt<1>("h1")), UInt<1>("h1"))) + mem_0_1.OEB1 <= not(and(and(not(UInt<1>("h1")), W0_en), UInt<1>("h1"))) mem_0_1.WEB1 <= not(and(and(UInt<1>("h1"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB1 <= not(and(W0_en, UInt<1>("h1"))) mem_0_0.CE2 <= R0_clk mem_0_0.A2 <= R0_addr node R0_data_0_0 = bits(mem_0_0.O2, 21, 0) mem_0_0.I2 is invalid - mem_0_0.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1"))) + mem_0_0.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), UInt<1>("h1"))) mem_0_0.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_0.CSB2 <= not(and(R0_en, UInt<1>("h1"))) mem_0_1.CE2 <= R0_clk mem_0_1.A2 <= R0_addr node R0_data_0_1 = bits(mem_0_1.O2, 17, 0) mem_0_1.I2 is invalid - mem_0_1.OEB2 <= not(and(not(UInt<1>("h0")), UInt<1>("h1"))) + mem_0_1.OEB2 <= not(and(and(not(UInt<1>("h0")), R0_en), UInt<1>("h1"))) mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB2 <= not(and(R0_en, UInt<1>("h1"))) node R0_data_0 = cat(R0_data_0_1, R0_data_0_0) @@ -842,224 +842,224 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 0, 0) mem_0_0.I <= bits(RW0_wdata, 0, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 0, 0) mem_0_1.I <= bits(RW0_wdata, 1, 1) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_2.CE <= RW0_clk mem_0_2.A <= RW0_addr node RW0_rdata_0_2 = bits(mem_0_2.O, 0, 0) mem_0_2.I <= bits(RW0_wdata, 2, 2) - mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_2.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))) mem_0_2.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_3.CE <= RW0_clk mem_0_3.A <= RW0_addr node RW0_rdata_0_3 = bits(mem_0_3.O, 0, 0) mem_0_3.I <= bits(RW0_wdata, 3, 3) - mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_3.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))) mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_4.CE <= RW0_clk mem_0_4.A <= RW0_addr node RW0_rdata_0_4 = bits(mem_0_4.O, 0, 0) mem_0_4.I <= bits(RW0_wdata, 4, 4) - mem_0_4.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_4.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_4.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1"))) mem_0_4.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_5.CE <= RW0_clk mem_0_5.A <= RW0_addr node RW0_rdata_0_5 = bits(mem_0_5.O, 0, 0) mem_0_5.I <= bits(RW0_wdata, 5, 5) - mem_0_5.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_5.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_5.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1"))) mem_0_5.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_6.CE <= RW0_clk mem_0_6.A <= RW0_addr node RW0_rdata_0_6 = bits(mem_0_6.O, 0, 0) mem_0_6.I <= bits(RW0_wdata, 6, 6) - mem_0_6.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_6.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_6.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1"))) mem_0_6.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_7.CE <= RW0_clk mem_0_7.A <= RW0_addr node RW0_rdata_0_7 = bits(mem_0_7.O, 0, 0) mem_0_7.I <= bits(RW0_wdata, 7, 7) - mem_0_7.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_7.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_7.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1"))) mem_0_7.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_8.CE <= RW0_clk mem_0_8.A <= RW0_addr node RW0_rdata_0_8 = bits(mem_0_8.O, 0, 0) mem_0_8.I <= bits(RW0_wdata, 8, 8) - mem_0_8.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_8.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_8.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 8, 8)), UInt<1>("h1"))) mem_0_8.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_9.CE <= RW0_clk mem_0_9.A <= RW0_addr node RW0_rdata_0_9 = bits(mem_0_9.O, 0, 0) mem_0_9.I <= bits(RW0_wdata, 9, 9) - mem_0_9.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_9.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_9.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 9, 9)), UInt<1>("h1"))) mem_0_9.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_10.CE <= RW0_clk mem_0_10.A <= RW0_addr node RW0_rdata_0_10 = bits(mem_0_10.O, 0, 0) mem_0_10.I <= bits(RW0_wdata, 10, 10) - mem_0_10.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_10.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_10.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 10, 10)), UInt<1>("h1"))) mem_0_10.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_11.CE <= RW0_clk mem_0_11.A <= RW0_addr node RW0_rdata_0_11 = bits(mem_0_11.O, 0, 0) mem_0_11.I <= bits(RW0_wdata, 11, 11) - mem_0_11.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_11.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_11.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 11, 11)), UInt<1>("h1"))) mem_0_11.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_12.CE <= RW0_clk mem_0_12.A <= RW0_addr node RW0_rdata_0_12 = bits(mem_0_12.O, 0, 0) mem_0_12.I <= bits(RW0_wdata, 12, 12) - mem_0_12.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_12.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_12.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 12, 12)), UInt<1>("h1"))) mem_0_12.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_13.CE <= RW0_clk mem_0_13.A <= RW0_addr node RW0_rdata_0_13 = bits(mem_0_13.O, 0, 0) mem_0_13.I <= bits(RW0_wdata, 13, 13) - mem_0_13.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_13.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_13.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 13, 13)), UInt<1>("h1"))) mem_0_13.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_14.CE <= RW0_clk mem_0_14.A <= RW0_addr node RW0_rdata_0_14 = bits(mem_0_14.O, 0, 0) mem_0_14.I <= bits(RW0_wdata, 14, 14) - mem_0_14.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_14.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_14.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 14, 14)), UInt<1>("h1"))) mem_0_14.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_15.CE <= RW0_clk mem_0_15.A <= RW0_addr node RW0_rdata_0_15 = bits(mem_0_15.O, 0, 0) mem_0_15.I <= bits(RW0_wdata, 15, 15) - mem_0_15.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_15.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_15.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 15, 15)), UInt<1>("h1"))) mem_0_15.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_16.CE <= RW0_clk mem_0_16.A <= RW0_addr node RW0_rdata_0_16 = bits(mem_0_16.O, 0, 0) mem_0_16.I <= bits(RW0_wdata, 16, 16) - mem_0_16.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_16.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_16.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 16, 16)), UInt<1>("h1"))) mem_0_16.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_17.CE <= RW0_clk mem_0_17.A <= RW0_addr node RW0_rdata_0_17 = bits(mem_0_17.O, 0, 0) mem_0_17.I <= bits(RW0_wdata, 17, 17) - mem_0_17.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_17.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_17.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 17, 17)), UInt<1>("h1"))) mem_0_17.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_18.CE <= RW0_clk mem_0_18.A <= RW0_addr node RW0_rdata_0_18 = bits(mem_0_18.O, 0, 0) mem_0_18.I <= bits(RW0_wdata, 18, 18) - mem_0_18.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_18.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_18.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 18, 18)), UInt<1>("h1"))) mem_0_18.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_19.CE <= RW0_clk mem_0_19.A <= RW0_addr node RW0_rdata_0_19 = bits(mem_0_19.O, 0, 0) mem_0_19.I <= bits(RW0_wdata, 19, 19) - mem_0_19.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_19.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_19.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 19, 19)), UInt<1>("h1"))) mem_0_19.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_20.CE <= RW0_clk mem_0_20.A <= RW0_addr node RW0_rdata_0_20 = bits(mem_0_20.O, 0, 0) mem_0_20.I <= bits(RW0_wdata, 20, 20) - mem_0_20.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_20.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_20.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 20, 20)), UInt<1>("h1"))) mem_0_20.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_21.CE <= RW0_clk mem_0_21.A <= RW0_addr node RW0_rdata_0_21 = bits(mem_0_21.O, 0, 0) mem_0_21.I <= bits(RW0_wdata, 21, 21) - mem_0_21.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_21.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_21.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 21, 21)), UInt<1>("h1"))) mem_0_21.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_22.CE <= RW0_clk mem_0_22.A <= RW0_addr node RW0_rdata_0_22 = bits(mem_0_22.O, 0, 0) mem_0_22.I <= bits(RW0_wdata, 22, 22) - mem_0_22.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_22.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_22.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 22, 22)), UInt<1>("h1"))) mem_0_22.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_23.CE <= RW0_clk mem_0_23.A <= RW0_addr node RW0_rdata_0_23 = bits(mem_0_23.O, 0, 0) mem_0_23.I <= bits(RW0_wdata, 23, 23) - mem_0_23.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_23.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_23.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 23, 23)), UInt<1>("h1"))) mem_0_23.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_24.CE <= RW0_clk mem_0_24.A <= RW0_addr node RW0_rdata_0_24 = bits(mem_0_24.O, 0, 0) mem_0_24.I <= bits(RW0_wdata, 24, 24) - mem_0_24.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_24.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_24.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 24, 24)), UInt<1>("h1"))) mem_0_24.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_25.CE <= RW0_clk mem_0_25.A <= RW0_addr node RW0_rdata_0_25 = bits(mem_0_25.O, 0, 0) mem_0_25.I <= bits(RW0_wdata, 25, 25) - mem_0_25.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_25.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_25.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 25, 25)), UInt<1>("h1"))) mem_0_25.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_26.CE <= RW0_clk mem_0_26.A <= RW0_addr node RW0_rdata_0_26 = bits(mem_0_26.O, 0, 0) mem_0_26.I <= bits(RW0_wdata, 26, 26) - mem_0_26.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_26.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_26.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 26, 26)), UInt<1>("h1"))) mem_0_26.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_27.CE <= RW0_clk mem_0_27.A <= RW0_addr node RW0_rdata_0_27 = bits(mem_0_27.O, 0, 0) mem_0_27.I <= bits(RW0_wdata, 27, 27) - mem_0_27.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_27.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_27.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 27, 27)), UInt<1>("h1"))) mem_0_27.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_28.CE <= RW0_clk mem_0_28.A <= RW0_addr node RW0_rdata_0_28 = bits(mem_0_28.O, 0, 0) mem_0_28.I <= bits(RW0_wdata, 28, 28) - mem_0_28.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_28.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_28.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 28, 28)), UInt<1>("h1"))) mem_0_28.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_29.CE <= RW0_clk mem_0_29.A <= RW0_addr node RW0_rdata_0_29 = bits(mem_0_29.O, 0, 0) mem_0_29.I <= bits(RW0_wdata, 29, 29) - mem_0_29.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_29.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_29.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 29, 29)), UInt<1>("h1"))) mem_0_29.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_30.CE <= RW0_clk mem_0_30.A <= RW0_addr node RW0_rdata_0_30 = bits(mem_0_30.O, 0, 0) mem_0_30.I <= bits(RW0_wdata, 30, 30) - mem_0_30.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_30.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_30.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 30, 30)), UInt<1>("h1"))) mem_0_30.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_31.CE <= RW0_clk mem_0_31.A <= RW0_addr node RW0_rdata_0_31 = bits(mem_0_31.O, 0, 0) mem_0_31.I <= bits(RW0_wdata, 31, 31) - mem_0_31.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_31.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1"))) mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))))))))))))))))))))))))))))))) @@ -1110,224 +1110,224 @@ circuit smem_0_ext : mem_0_0.A <= RW0_addr node RW0_rdata_0_0 = bits(mem_0_0.O, 0, 0) mem_0_0.I <= bits(RW0_wdata, 0, 0) - mem_0_0.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_0.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_0.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 0, 0)), UInt<1>("h1"))) mem_0_0.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_1.CE <= RW0_clk mem_0_1.A <= RW0_addr node RW0_rdata_0_1 = bits(mem_0_1.O, 0, 0) mem_0_1.I <= bits(RW0_wdata, 1, 1) - mem_0_1.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_1.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_1.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 1, 1)), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_2.CE <= RW0_clk mem_0_2.A <= RW0_addr node RW0_rdata_0_2 = bits(mem_0_2.O, 0, 0) mem_0_2.I <= bits(RW0_wdata, 2, 2) - mem_0_2.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_2.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_2.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 2, 2)), UInt<1>("h1"))) mem_0_2.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_3.CE <= RW0_clk mem_0_3.A <= RW0_addr node RW0_rdata_0_3 = bits(mem_0_3.O, 0, 0) mem_0_3.I <= bits(RW0_wdata, 3, 3) - mem_0_3.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_3.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))) mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_4.CE <= RW0_clk mem_0_4.A <= RW0_addr node RW0_rdata_0_4 = bits(mem_0_4.O, 0, 0) mem_0_4.I <= bits(RW0_wdata, 4, 4) - mem_0_4.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_4.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_4.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 4, 4)), UInt<1>("h1"))) mem_0_4.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_5.CE <= RW0_clk mem_0_5.A <= RW0_addr node RW0_rdata_0_5 = bits(mem_0_5.O, 0, 0) mem_0_5.I <= bits(RW0_wdata, 5, 5) - mem_0_5.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_5.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_5.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 5, 5)), UInt<1>("h1"))) mem_0_5.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_6.CE <= RW0_clk mem_0_6.A <= RW0_addr node RW0_rdata_0_6 = bits(mem_0_6.O, 0, 0) mem_0_6.I <= bits(RW0_wdata, 6, 6) - mem_0_6.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_6.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_6.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 6, 6)), UInt<1>("h1"))) mem_0_6.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_7.CE <= RW0_clk mem_0_7.A <= RW0_addr node RW0_rdata_0_7 = bits(mem_0_7.O, 0, 0) mem_0_7.I <= bits(RW0_wdata, 7, 7) - mem_0_7.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_7.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_7.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1"))) mem_0_7.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_8.CE <= RW0_clk mem_0_8.A <= RW0_addr node RW0_rdata_0_8 = bits(mem_0_8.O, 0, 0) mem_0_8.I <= bits(RW0_wdata, 8, 8) - mem_0_8.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_8.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_8.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 8, 8)), UInt<1>("h1"))) mem_0_8.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_9.CE <= RW0_clk mem_0_9.A <= RW0_addr node RW0_rdata_0_9 = bits(mem_0_9.O, 0, 0) mem_0_9.I <= bits(RW0_wdata, 9, 9) - mem_0_9.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_9.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_9.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 9, 9)), UInt<1>("h1"))) mem_0_9.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_10.CE <= RW0_clk mem_0_10.A <= RW0_addr node RW0_rdata_0_10 = bits(mem_0_10.O, 0, 0) mem_0_10.I <= bits(RW0_wdata, 10, 10) - mem_0_10.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_10.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_10.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 10, 10)), UInt<1>("h1"))) mem_0_10.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_11.CE <= RW0_clk mem_0_11.A <= RW0_addr node RW0_rdata_0_11 = bits(mem_0_11.O, 0, 0) mem_0_11.I <= bits(RW0_wdata, 11, 11) - mem_0_11.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_11.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_11.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 11, 11)), UInt<1>("h1"))) mem_0_11.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_12.CE <= RW0_clk mem_0_12.A <= RW0_addr node RW0_rdata_0_12 = bits(mem_0_12.O, 0, 0) mem_0_12.I <= bits(RW0_wdata, 12, 12) - mem_0_12.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_12.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_12.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 12, 12)), UInt<1>("h1"))) mem_0_12.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_13.CE <= RW0_clk mem_0_13.A <= RW0_addr node RW0_rdata_0_13 = bits(mem_0_13.O, 0, 0) mem_0_13.I <= bits(RW0_wdata, 13, 13) - mem_0_13.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_13.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_13.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 13, 13)), UInt<1>("h1"))) mem_0_13.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_14.CE <= RW0_clk mem_0_14.A <= RW0_addr node RW0_rdata_0_14 = bits(mem_0_14.O, 0, 0) mem_0_14.I <= bits(RW0_wdata, 14, 14) - mem_0_14.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_14.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_14.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 14, 14)), UInt<1>("h1"))) mem_0_14.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_15.CE <= RW0_clk mem_0_15.A <= RW0_addr node RW0_rdata_0_15 = bits(mem_0_15.O, 0, 0) mem_0_15.I <= bits(RW0_wdata, 15, 15) - mem_0_15.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_15.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_15.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 15, 15)), UInt<1>("h1"))) mem_0_15.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_16.CE <= RW0_clk mem_0_16.A <= RW0_addr node RW0_rdata_0_16 = bits(mem_0_16.O, 0, 0) mem_0_16.I <= bits(RW0_wdata, 16, 16) - mem_0_16.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_16.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_16.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 16, 16)), UInt<1>("h1"))) mem_0_16.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_17.CE <= RW0_clk mem_0_17.A <= RW0_addr node RW0_rdata_0_17 = bits(mem_0_17.O, 0, 0) mem_0_17.I <= bits(RW0_wdata, 17, 17) - mem_0_17.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_17.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_17.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 17, 17)), UInt<1>("h1"))) mem_0_17.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_18.CE <= RW0_clk mem_0_18.A <= RW0_addr node RW0_rdata_0_18 = bits(mem_0_18.O, 0, 0) mem_0_18.I <= bits(RW0_wdata, 18, 18) - mem_0_18.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_18.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_18.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 18, 18)), UInt<1>("h1"))) mem_0_18.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_19.CE <= RW0_clk mem_0_19.A <= RW0_addr node RW0_rdata_0_19 = bits(mem_0_19.O, 0, 0) mem_0_19.I <= bits(RW0_wdata, 19, 19) - mem_0_19.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_19.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_19.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 19, 19)), UInt<1>("h1"))) mem_0_19.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_20.CE <= RW0_clk mem_0_20.A <= RW0_addr node RW0_rdata_0_20 = bits(mem_0_20.O, 0, 0) mem_0_20.I <= bits(RW0_wdata, 20, 20) - mem_0_20.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_20.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_20.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 20, 20)), UInt<1>("h1"))) mem_0_20.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_21.CE <= RW0_clk mem_0_21.A <= RW0_addr node RW0_rdata_0_21 = bits(mem_0_21.O, 0, 0) mem_0_21.I <= bits(RW0_wdata, 21, 21) - mem_0_21.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_21.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_21.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 21, 21)), UInt<1>("h1"))) mem_0_21.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_22.CE <= RW0_clk mem_0_22.A <= RW0_addr node RW0_rdata_0_22 = bits(mem_0_22.O, 0, 0) mem_0_22.I <= bits(RW0_wdata, 22, 22) - mem_0_22.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_22.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_22.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 22, 22)), UInt<1>("h1"))) mem_0_22.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_23.CE <= RW0_clk mem_0_23.A <= RW0_addr node RW0_rdata_0_23 = bits(mem_0_23.O, 0, 0) mem_0_23.I <= bits(RW0_wdata, 23, 23) - mem_0_23.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_23.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_23.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 23, 23)), UInt<1>("h1"))) mem_0_23.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_24.CE <= RW0_clk mem_0_24.A <= RW0_addr node RW0_rdata_0_24 = bits(mem_0_24.O, 0, 0) mem_0_24.I <= bits(RW0_wdata, 24, 24) - mem_0_24.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_24.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_24.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 24, 24)), UInt<1>("h1"))) mem_0_24.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_25.CE <= RW0_clk mem_0_25.A <= RW0_addr node RW0_rdata_0_25 = bits(mem_0_25.O, 0, 0) mem_0_25.I <= bits(RW0_wdata, 25, 25) - mem_0_25.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_25.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_25.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 25, 25)), UInt<1>("h1"))) mem_0_25.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_26.CE <= RW0_clk mem_0_26.A <= RW0_addr node RW0_rdata_0_26 = bits(mem_0_26.O, 0, 0) mem_0_26.I <= bits(RW0_wdata, 26, 26) - mem_0_26.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_26.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_26.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 26, 26)), UInt<1>("h1"))) mem_0_26.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_27.CE <= RW0_clk mem_0_27.A <= RW0_addr node RW0_rdata_0_27 = bits(mem_0_27.O, 0, 0) mem_0_27.I <= bits(RW0_wdata, 27, 27) - mem_0_27.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_27.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_27.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 27, 27)), UInt<1>("h1"))) mem_0_27.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_28.CE <= RW0_clk mem_0_28.A <= RW0_addr node RW0_rdata_0_28 = bits(mem_0_28.O, 0, 0) mem_0_28.I <= bits(RW0_wdata, 28, 28) - mem_0_28.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_28.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_28.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 28, 28)), UInt<1>("h1"))) mem_0_28.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_29.CE <= RW0_clk mem_0_29.A <= RW0_addr node RW0_rdata_0_29 = bits(mem_0_29.O, 0, 0) mem_0_29.I <= bits(RW0_wdata, 29, 29) - mem_0_29.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_29.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_29.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 29, 29)), UInt<1>("h1"))) mem_0_29.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_30.CE <= RW0_clk mem_0_30.A <= RW0_addr node RW0_rdata_0_30 = bits(mem_0_30.O, 0, 0) mem_0_30.I <= bits(RW0_wdata, 30, 30) - mem_0_30.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_30.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_30.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 30, 30)), UInt<1>("h1"))) mem_0_30.CSB <= not(and(RW0_en, UInt<1>("h1"))) mem_0_31.CE <= RW0_clk mem_0_31.A <= RW0_addr node RW0_rdata_0_31 = bits(mem_0_31.O, 0, 0) mem_0_31.I <= bits(RW0_wdata, 31, 31) - mem_0_31.OEB <= not(and(not(RW0_wmode), UInt<1>("h1"))) + mem_0_31.OEB <= not(and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))) mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1"))) mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))))))))))))))))))))))))))))))) diff --git a/macros/src/test/scala/SynFlops.scala b/macros/src/test/scala/SynFlops.scala index 8198d8f3..0723bb33 100644 --- a/macros/src/test/scala/SynFlops.scala +++ b/macros/src/test/scala/SynFlops.scala @@ -11,7 +11,7 @@ s""" mem_0_0.${libPortPrefix}_addr <= ${libPortPrefix}_addr node ${libPortPrefix}_dout_0_0 = bits(mem_0_0.${libPortPrefix}_dout, ${libWidth-1}, 0) mem_0_0.${libPortPrefix}_din <= bits(${libPortPrefix}_din, ${libWidth-1}, 0) - mem_0_0.${libPortPrefix}_write_en <= and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.${libPortPrefix}_write_en <= and(and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node ${libPortPrefix}_dout_0 = ${libPortPrefix}_dout_0_0 ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<1>("h0")) @@ -148,7 +148,7 @@ circuit target_memory : mem_0_0.innerB_clk <= outerA_clk mem_0_0.innerB_addr <= outerA_addr mem_0_0.innerB_din <= bits(outerA_din, 7, 0) - mem_0_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) + mem_0_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h0"))) mem_0_0.innerA_clk <= outerB_clk mem_0_0.innerA_addr <= outerB_addr node outerB_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0) @@ -157,7 +157,7 @@ circuit target_memory : mem_1_0.innerB_clk <= outerA_clk mem_1_0.innerB_addr <= outerA_addr mem_1_0.innerB_din <= bits(outerA_din, 7, 0) - mem_1_0.innerB_write_en <= and(and(outerA_write_en, UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) + mem_1_0.innerB_write_en <= and(and(and(outerA_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outerA_addr_sel, UInt<1>("h1"))) mem_1_0.innerA_clk <= outerB_clk mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) @@ -182,7 +182,7 @@ circuit target_memory : mem_0_0.innerB_clk <= innerB_clk mem_0_0.innerB_addr <= innerB_addr mem_0_0.innerB_din <= bits(innerB_din, 7, 0) - mem_0_0.innerB_write_en <= and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1")) + mem_0_0.innerB_write_en <= and(and(and(innerB_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) mem_0_0.innerA_clk <= innerA_clk mem_0_0.innerA_addr <= innerA_addr node innerA_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0) diff --git a/mdf b/mdf index 515dda51..4281e8f6 160000 --- a/mdf +++ b/mdf @@ -1 +1 @@ -Subproject commit 515dda51206eb40bcbe902700abc8ca36b141c0d +Subproject commit 4281e8f621decc10a8cdb878c593e46115c70998 diff --git a/tapeout/src/main/scala/transforms/ResetInverter.scala b/tapeout/src/main/scala/transforms/ResetInverter.scala index da090dbf..08d84983 100644 --- a/tapeout/src/main/scala/transforms/ResetInverter.scala +++ b/tapeout/src/main/scala/transforms/ResetInverter.scala @@ -34,11 +34,12 @@ object ResetN extends Pass { mod.copy(ports = portsx, body = bodyx) } - def run(c: Circuit): Circuit = + def run(c: Circuit): Circuit = { c.copy(modules = c.modules map { case mod: Module if mod.name == c.main => invertReset(mod) case other => other }) + } } class ResetInverterTransform extends Transform { diff --git a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala index 7abcbf4c..07fca302 100644 --- a/tapeout/src/test/scala/transforms/ResetInverterSpec.scala +++ b/tapeout/src/test/scala/transforms/ResetInverterSpec.scala @@ -22,7 +22,7 @@ class ResetNSpec extends FreeSpec with Matchers { "Inverting reset needs to be done throughout module" in { val optionsManager = new ExecutionOptionsManager("dsptools") with HasChiselExecutionOptions with HasFirrtlOptions { - firrtlOptions = firrtlOptions.copy(compilerName = "low") + firrtlOptions = firrtlOptions.copy(compilerName = "low", customTransforms = List(new ResetInverterTransform)), } chisel3.Driver.execute(optionsManager, () => new ExampleModuleNeedsResetInverted) match { case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, firrtl))) => diff --git a/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala b/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala index 7c634837..76223b71 100644 --- a/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala +++ b/tapeout/src/test/scala/transforms/retime/RetimeSpec.scala @@ -27,10 +27,10 @@ class RetimeSpec extends FlatSpec with Matchers { val dir = uniqueDirName(gen, "RetimeModule") chisel3.Driver.execute(Array("-td", s"test_run_dir/$dir", "-foaf", s"test_run_dir/$dir/final"), gen) shouldBe a [ChiselExecutionSuccess] - val lines = io.Source.fromFile(s"test_run_dir/$dir/final.anno.json").getLines().map(normalized).mkString("\n") + val lines = io.Source.fromFile(s"test_run_dir/$dir/test_run_dir/$dir/final.anno.json").getLines().map(normalized).mkString("\n") lines should include("barstools.tapeout.transforms.retime.RetimeTransform") } - + // TODO(azidar): need to fix/add instance annotations ignore should "pass simple retime instance annotation" in { val gen = () => new RetimeInstance() From 5fcae018256a5f9992ce95f514928b61a988c83b Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 19 Feb 2020 18:52:48 -0800 Subject: [PATCH 3/3] Fix width of zeros after #74 --- macros/src/test/scala/CostFunction.scala | 2 +- macros/src/test/scala/MultiPort.scala | 10 +++---- macros/src/test/scala/SimpleSplitDepth.scala | 10 +++---- macros/src/test/scala/SimpleSplitWidth.scala | 6 ++--- macros/src/test/scala/SpecificExamples.scala | 28 ++++++++++---------- macros/src/test/scala/SynFlops.scala | 10 +++---- 6 files changed, 33 insertions(+), 33 deletions(-) diff --git a/macros/src/test/scala/CostFunction.scala b/macros/src/test/scala/CostFunction.scala index 35936ed1..b8a27f7f 100644 --- a/macros/src/test/scala/CostFunction.scala +++ b/macros/src/test/scala/CostFunction.scala @@ -99,7 +99,7 @@ circuit target_memory : mem_0_3.din <= bits(din, 127, 96) mem_0_3.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node dout_0 = cat(dout_0_3, cat(dout_0_2, cat(dout_0_1, dout_0_0))) - dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0")) + dout <= mux(UInt<1>("h1"), dout_0, UInt<128>("h0")) extmodule SRAM_WIDTH_32 : input addr : UInt<10> diff --git a/macros/src/test/scala/MultiPort.scala b/macros/src/test/scala/MultiPort.scala index fdaae9f7..3899f835 100644 --- a/macros/src/test/scala/MultiPort.scala +++ b/macros/src/test/scala/MultiPort.scala @@ -111,8 +111,8 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim mem_0_3.portB_read_en <= and(portB_read_en, UInt<1>("h1")) mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1")) node portB_dout_0 = cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0))) - portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0")) - portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0")) + portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<64>("h0")) + portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<64>("h0")) """ compileExecuteAndTest(mem, lib, v, output) @@ -215,7 +215,7 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS node portA_dout_0_3 = bits(mem_0_3.portA_dout, 15, 0) mem_0_3.portA_read_en <= and(portA_read_en, UInt<1>("h1")) node portA_dout_0 = cat(portA_dout_0_3, cat(portA_dout_0_2, cat(portA_dout_0_1, portA_dout_0_0))) - portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0")) + portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<64>("h0")) """ compileExecuteAndTest(mem, lib, v, output) @@ -384,8 +384,8 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera mem_0_7.portB_read_en <= and(portB_read_en, UInt<1>("h1")) mem_0_7.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 7, 7)), UInt<1>("h1")) node portB_dout_0 = cat(portB_dout_0_7, cat(portB_dout_0_6, cat(portB_dout_0_5, cat(portB_dout_0_4, cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0))))))) - portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0")) - portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0")) + portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<64>("h0")) + portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<64>("h0")) """ compileExecuteAndTest(mem, lib, v, output) diff --git a/macros/src/test/scala/SimpleSplitDepth.scala b/macros/src/test/scala/SimpleSplitDepth.scala index 8df8ec7e..e3560f9a 100644 --- a/macros/src/test/scala/SimpleSplitDepth.scala +++ b/macros/src/test/scala/SimpleSplitDepth.scala @@ -48,7 +48,7 @@ s""" } def generate_outer_dout_tree(i:Int, depthInstances: Int): String = { if (i > depthInstances - 1) { - "UInt<1>(\"h0\")" + s"""UInt<${libWidth}>("h0")""" } else { s"""mux(eq(${memPortPrefix}_addr_sel_reg, UInt<%d>("h%s")), ${memPortPrefix}_dout_%d, %s)""".format( selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, depthInstances) @@ -59,7 +59,7 @@ s""" if (selectBits > 0) { output append generate_outer_dout_tree(0, depthInstances) } else { - output append s"""mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<1>("h0"))""" + output append s"""mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<${libWidth}>("h0"))""" } output.toString @@ -287,7 +287,7 @@ circuit target_memory : mem_1_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1"))) node outer_dout_1 = outer_dout_1_0 - outer_dout <= mux(eq(outer_addr_sel_reg, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel_reg, UInt<1>("h1")), outer_dout_1, UInt<1>("h0"))) + outer_dout <= mux(eq(outer_addr_sel_reg, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel_reg, UInt<1>("h1")), outer_dout_1, UInt<8>("h0"))) extmodule awesome_lib_mem : input lib_addr : UInt<10> input lib_clk : Clock @@ -378,7 +378,7 @@ circuit target_memory : mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) node outerB_dout_1 = outerB_dout_1_0 - outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0"))) + outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0"))) extmodule awesome_lib_mem : input innerA_addr : UInt<10> @@ -542,7 +542,7 @@ circuit target_memory : mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) node outerB_dout_1 = outerB_dout_1_0 - outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0"))) + outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0"))) extmodule awesome_lib_mem : input innerA_addr : UInt<10> diff --git a/macros/src/test/scala/SimpleSplitWidth.scala b/macros/src/test/scala/SimpleSplitWidth.scala index 9cc10f9d..843eed49 100644 --- a/macros/src/test/scala/SimpleSplitWidth.scala +++ b/macros/src/test/scala/SimpleSplitWidth.scala @@ -63,7 +63,7 @@ s""" output append s""" - ${memPortPrefix}_dout <= mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<1>("h0")) + ${memPortPrefix}_dout <= mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<${memWidth}>("h0")) """ output.toString } @@ -438,7 +438,7 @@ class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGen mem_0_3.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1")) mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))) - outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) + outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<32>("h0")) """ compileExecuteAndTest(mem, lib, v, output) @@ -536,7 +536,7 @@ class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAM mem_0_3.lib_read_en <= and(outer_read_en, UInt<1>("h1")) mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))) - outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0")) + outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<32>("h0")) """ compileExecuteAndTest(mem, lib, v, output) diff --git a/macros/src/test/scala/SpecificExamples.scala b/macros/src/test/scala/SpecificExamples.scala index 56f4500f..e41932bb 100644 --- a/macros/src/test/scala/SpecificExamples.scala +++ b/macros/src/test/scala/SpecificExamples.scala @@ -76,7 +76,7 @@ circuit cc_banks_0_ext : mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1")) mem_0_0.wen <= and(and(and(RW0_wmode, RW0_en), UInt<1>("h1")), UInt<1>("h1")) node RW0_rdata_0 = RW0_rdata_0_0 - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0")) extmodule fake_mem : input addr : UInt<12> @@ -159,7 +159,7 @@ circuit cc_dir_ext : mem_0_1.mport <= not(cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), bits(RW0_wmask, 4, 4))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) mem_0_1.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1")) node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<128>("h0")) extmodule fake_mem : input addr : UInt<9> @@ -486,7 +486,7 @@ circuit smem_0_ext : mem_1_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1")))) mem_1_3.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1")))) node R0_data_1 = cat(R0_data_1_3, cat(R0_data_1_2, cat(R0_data_1_1, R0_data_1_0))) - R0_data <= mux(eq(R0_addr_sel_reg, UInt<1>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<1>("h1")), R0_data_1, UInt<1>("h0"))) + R0_data <= mux(eq(R0_addr_sel_reg, UInt<1>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<1>("h1")), R0_data_1, UInt<88>("h0"))) module _T_84_ext : @@ -621,7 +621,7 @@ circuit smem_0_ext : mem_3_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h3")))) mem_3_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h3")))) node R0_data_3 = cat(R0_data_3_1, R0_data_3_0) - R0_data <= mux(eq(R0_addr_sel_reg, UInt<2>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<2>("h1")), R0_data_1, mux(eq(R0_addr_sel_reg, UInt<2>("h2")), R0_data_2, mux(eq(R0_addr_sel_reg, UInt<2>("h3")), R0_data_3, UInt<1>("h0"))))) + R0_data <= mux(eq(R0_addr_sel_reg, UInt<2>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<2>("h1")), R0_data_1, mux(eq(R0_addr_sel_reg, UInt<2>("h2")), R0_data_2, mux(eq(R0_addr_sel_reg, UInt<2>("h3")), R0_data_3, UInt<64>("h0"))))) extmodule my_sram_2rw_128x32 : input A1 : UInt<7> @@ -684,7 +684,7 @@ circuit smem_0_ext : mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))) mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<80>("h0")) extmodule my_sram_1rw_64x32 : input A : UInt<6> @@ -723,7 +723,7 @@ circuit smem_0_ext : mem_0_1.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0")) extmodule my_sram_1rw_512x32 : input A : UInt<9> @@ -776,7 +776,7 @@ circuit smem_0_ext : mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1"))) mem_0_1.CSB2 <= not(and(R0_en, UInt<1>("h1"))) node R0_data_0 = cat(R0_data_0_1, R0_data_0_0) - R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0")) + R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<40>("h0")) extmodule my_sram_2rw_32x22 : input A1 : UInt<5> @@ -1063,7 +1063,7 @@ circuit smem_0_ext : mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1"))) mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))))))))))))))))))))))))))))))) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<32>("h0")) module smem_0_ext : input RW0_addr : UInt<6> @@ -1331,7 +1331,7 @@ circuit smem_0_ext : mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1"))) mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1"))) node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))))))))))))))))))))))))))))))) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<32>("h0")) extmodule my_sram_1rw_64x8 : input A : UInt<6> @@ -1375,7 +1375,7 @@ class SmallTagArrayTest extends MacroCompilerSpec with HasSRAMGenerator with Has | mem_0_0.mask <= cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), bits(mask, 0, 0)))))))))))))))))))))))))))))))) | mem_0_0.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1")) | node dout_0 = dout_0_0 - | dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0")) + | dout <= mux(UInt<1>("h1"), dout_0, UInt<26>("h0")) """.stripMargin compileExecuteAndTest(mem, lib, v, output) @@ -1573,7 +1573,7 @@ circuit T_2172_ext : mem_0_3.din <= bits(RW0_wdata, 79, 60) mem_0_3.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")) node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<80>("h0")) extmodule SRAM1RW64x32 : input addr : UInt<6> @@ -1605,7 +1605,7 @@ circuit T_2172_ext : mem_0_1.din <= bits(RW0_wdata, 63, 32) mem_0_1.write_en <= and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")) node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0")) extmodule SRAM1RW512x32 : input addr : UInt<9> @@ -1675,7 +1675,7 @@ circuit T_2172_ext : mem_0_7.din <= bits(RW0_wdata, 63, 56) mem_0_7.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1")) node RW0_rdata_0 = cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0))))))) - RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0")) + RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0")) extmodule SRAM1RW512x8 : input addr : UInt<9> @@ -1731,7 +1731,7 @@ circuit T_2172_ext : mem_0_3.portA_addr <= R0_addr node R0_data_0_3 = bits(mem_0_3.portA_dout, 21, 0) node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0))) - R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0")) + R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<88>("h0")) extmodule SRAM2RW64x32 : input portA_addr : UInt<6> diff --git a/macros/src/test/scala/SynFlops.scala b/macros/src/test/scala/SynFlops.scala index 0723bb33..f12161a1 100644 --- a/macros/src/test/scala/SynFlops.scala +++ b/macros/src/test/scala/SynFlops.scala @@ -13,7 +13,7 @@ s""" mem_0_0.${libPortPrefix}_din <= bits(${libPortPrefix}_din, ${libWidth-1}, 0) mem_0_0.${libPortPrefix}_write_en <= and(and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1")) node ${libPortPrefix}_dout_0 = ${libPortPrefix}_dout_0_0 - ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<1>("h0")) + ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<${libWidth}>("h0")) module split_${lib_name} : input ${libPortPrefix}_addr : UInt<${lib_addr_width}> @@ -162,7 +162,7 @@ circuit target_memory : mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) node outerB_dout_1 = outerB_dout_1_0 - outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0"))) + outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0"))) """ override def generateFooterPorts = @@ -187,7 +187,7 @@ circuit target_memory : mem_0_0.innerA_addr <= innerA_addr node innerA_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0) node innerA_dout_0 = innerA_dout_0_0 - innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<1>("h0")) + innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<8>("h0")) module split_awesome_lib_mem : input innerA_addr : UInt<10> @@ -294,7 +294,7 @@ circuit target_memory : mem_1_0.innerA_addr <= outerB_addr node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0) node outerB_dout_1 = outerB_dout_1_0 - outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0"))) + outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0"))) """ override def generateFooterPorts = @@ -384,7 +384,7 @@ circuit target_memory : mem_0_7.innerA_addr <= innerA_addr node innerA_dout_0_7 = bits(mem_0_7.innerA_dout, 0, 0) node innerA_dout_0 = cat(innerA_dout_0_7, cat(innerA_dout_0_6, cat(innerA_dout_0_5, cat(innerA_dout_0_4, cat(innerA_dout_0_3, cat(innerA_dout_0_2, cat(innerA_dout_0_1, innerA_dout_0_0))))))) - innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<1>("h0")) + innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<8>("h0")) module split_awesome_lib_mem :