wu-arch/chipyard
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Bump sifive-blocks

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This commit is contained in:
Jerry Zhao
2020-05-05 13:58:01 -07:00
parent 9b94570648
commit 63c46d89c1
8 changed files with 1 additions and 49 deletions
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2
generators/chipyard/src/main/scala/config/ArianeConfigs.scala
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@@ -15,7 +15,6 @@ class ArianeConfig extends Config(
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing)
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing
new testchipip.WithTSI ++ // use testchipip serial offchip link
new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks)
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
@@ -31,7 +30,6 @@ class dmiArianeConfig extends Config(
new chipyard.iobinders.WithSimAXIMem ++
new chipyard.iobinders.WithTiedOffSerial ++
new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation
new chipyard.config.WithNoGPIO ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++