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Merge pull request #1349 from ucb-bar/misc-improv

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Small build system improvements
This commit is contained in:
Abraham Gonzalez
2023-02-16 11:40:55 -08:00
committed by GitHub
parent f77bb36510 aa02295a0b
commit 632a7a9348
6 changed files with 4 additions and 10 deletions
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2
common.mk
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@@ -17,7 +17,7 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog) \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler"

3
fpga/Makefile
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@@ -90,9 +90,6 @@ fpga_common_script_dir := $(fpga_dir)/common/tcl
######################################################################################### #########################################################################################
# setup misc. sim files # setup misc. sim files
######################################################################################### #########################################################################################
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
# copy files but ignore *.h files in *.f (match vcs) # copy files but ignore *.h files in *.f (match vcs)
$(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR) $(sim_files): $(SIM_FILE_REQS) | $(GEN_COLLATERAL_DIR)
cp -f $^ $(GEN_COLLATERAL_DIR) cp -f $^ $(GEN_COLLATERAL_DIR)

1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -51,6 +51,7 @@ class AbstractConfig extends Config(
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus
new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)

2
project/build.properties
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@@ -1 +1 @@
sbt.version=1.5.5 sbt.version=1.8.2

3
sims/common-sim-flags.mk
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@@ -33,6 +33,3 @@ SIM_LDFLAGS = \
-lfesvr \ -lfesvr \
-ldramsim \ -ldramsim \
$(EXTRA_SIM_LDFLAGS) $(EXTRA_SIM_LDFLAGS)
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v

3
vlsi/Makefile
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@@ -54,7 +54,7 @@ endif
######################################################################################### #########################################################################################
# general rules # general rules
######################################################################################### #########################################################################################
.PHONY: default .PHONY: default all
default: all default: all
all: drc lvs all: drc lvs
@@ -82,7 +82,6 @@ ifneq ($(CUSTOM_VLOG), )
else else
cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL) cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL)
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL) echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
endif endif
######################################################################################### #########################################################################################