wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Remove type casts; use a tuple match instead

Browse Source
This commit is contained in:
John Wright
2020-03-30 13:10:00 -07:00
parent a6731f6a5e
commit 62df79934e
1 changed files with 10 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
iocell/src/main/scala/chisel/IOCell.scala
View File

@@ -91,8 +91,8 @@ object IOCell {
outFn: () => DigitalOutIOCell = IOCell.genericOutput, outFn: () => DigitalOutIOCell = IOCell.genericOutput,
anaFn: () => AnalogIOCell = IOCell.genericAnalog): Seq[IOCell] = anaFn: () => AnalogIOCell = IOCell.genericAnalog): Seq[IOCell] =
{ {
coreSignal match { (coreSignal: T, padSignal: T) match {
case coreSignal: Analog => { case (coreSignal: Analog, padSignal: Analog) => {
if (coreSignal.getWidth == 0) { if (coreSignal.getWidth == 0) {
Seq() Seq()
} else { } else {
@@ -104,7 +104,7 @@ object IOCell {
Seq(iocell) Seq(iocell)
} }
} }
case coreSignal: Clock => { case (coreSignal: Clock, padSignal: Clock) => {
DataMirror.directionOf(coreSignal) match { DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => { case ActualDirection.Input => {
val iocell = inFn() val iocell = inFn()
@@ -125,7 +125,7 @@ object IOCell {
case _ => throw new Exception("Unknown direction") case _ => throw new Exception("Unknown direction")
} }
} }
case coreSignal: Bits => { case (coreSignal: Bits, padSignal: Bits) => {
require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width") require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width")
if (padSignal.getWidth == 0) { if (padSignal.getWidth == 0) {
// This dummy assignment will prevent invalid firrtl from being emitted // This dummy assignment will prevent invalid firrtl from being emitted
@@ -137,8 +137,7 @@ object IOCell {
} else { } else {
DataMirror.directionOf(coreSignal) match { DataMirror.directionOf(coreSignal) match {
case ActualDirection.Input => { case ActualDirection.Input => {
// this type cast is safe because we guarantee that padSignal and coreSignal are the same type (T), but the compiler is not smart enough to know that val iocells = padSignal.asBools.zipWithIndex.map { case (w, i) =>
val iocells = padSignal.asInstanceOf[Bits].asBools.zipWithIndex.map { case (w, i) =>
val iocell = inFn() val iocell = inFn()
name.foreach(n => iocell.suggestName(n + "_" + i)) name.foreach(n => iocell.suggestName(n + "_" + i))
iocell.io.pad := w iocell.io.pad := w
@@ -163,20 +162,16 @@ object IOCell {
} }
} }
} }
case coreSignal: Vec[Data] => { case (coreSignal: Vec[Data], padSignal: Vec[Data]) => {
// this type cast is safe because we guarantee that padSignal and coreSignal are the same type (T), but the compiler is not smart enough to know that require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
val padSignal2 = padSignal.asInstanceOf[Vec[Data]] coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
require(padSignal2.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same")
coreSignal.zip(padSignal2).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), inFn, outFn, anaFn) val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + i), inFn, outFn, anaFn)
total ++ ios total ++ ios
} }
} }
case coreSignal: Record => { case (coreSignal: Record, padSignal: Record) => {
// this type cast is safe because we guarantee that padSignal and coreSignal are the same type (T), but the compiler is not smart enough to know that
val padSignal2 = padSignal.asInstanceOf[Record]
coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) => coreSignal.elements.foldLeft(Seq.empty[IOCell]) { case (total, (eltName, core)) =>
val pad = padSignal2.elements(eltName) val pad = padSignal.elements(eltName)
val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), inFn, outFn, anaFn) val ios = IOCell.generateFromSignal(core, pad, name.map(_ + "_" + eltName), inFn, outFn, anaFn)
total ++ ios total ++ ios
} }