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Fix PassThroughClockGenerator to handle multiclock properly

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This commit is contained in:
Jerry Zhao
2023-05-10 23:34:29 -07:00
parent ffc4d1f662
commit 624785376a
1 changed files with 10 additions and 10 deletions
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20
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -103,20 +103,20 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
// This aggregate node should do nothing // This aggregate node should do nothing
val clockGroupAggNode = ClockGroupAggregateNode("fake") val clockGroupAggNode = ClockGroupAggregateNode("fake")
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
system.allClockGroupsNode :*= clockGroupAggNode := clockGroupsSourceNode system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
InModuleBody { InModuleBody {
val reset_io = IO(Input(AsyncReset())) val reset_io = IO(Input(AsyncReset()))
val clock_ios = clockGroupAggNode.out.map { case (bundle, edge) => require(clockGroupAggNode.out.size == 1)
val freqs = edge.sink.members.map(_.take.map(_.freqMHz)).flatten val (bundle, edge) = clockGroupAggNode.out(0)
require(freqs.distinct.size == 1)
val clock_io = IO(Input(new ClockWithFreq(freqs.head))).suggestName(s"clock_${edge.sink.name}") val clock_ios = (bundle.member.data zip edge.sink.members).map { case (b, m) =>
bundle.member.data.foreach { b => val freq = m.take.get.freqMHz
b.clock := clock_io.clock val clock_io = IO(Input(new ClockWithFreq(freq))).suggestName(s"clock_${m.name.get}")
b.reset := reset_io b.clock := clock_io.clock
} b.reset := reset_io
clock_io clock_io
} }.toSeq
((clock_ios :+ reset_io), Nil) ((clock_ios :+ reset_io), Nil)
} }
} }