From 61d094e887feabd2bab132cb8e0a8aaa4162ad1d Mon Sep 17 00:00:00 2001
From: Harrison Liew <harrisonliew@gmail.com>
Date: Wed, 8 Feb 2023 16:05:38 -0800
Subject: [PATCH] [skip ci] Add sv2v, sty. Fix Makefile rebuild. Using sv2v,
 but Yosys still fails.

---
 common.mk                |  2 +-
 conda-reqs/chipyard.yaml |  4 +++-
 vlsi/Makefile            | 50 ++++++++++++++++++++++++----------------
 vlsi/tutorial.mk         |  4 +++-
 4 files changed, 37 insertions(+), 23 deletions(-)

diff --git a/common.mk b/common.mk
index cddbf5b7..322e2724 100644
--- a/common.mk
+++ b/common.mk
@@ -194,7 +194,7 @@ endif
 		--disable-annotation-classless \
 		--disable-annotation-unknown \
 		--mlir-timing \
-		--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
+		--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
 		--repl-seq-mem \
 		--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
 		--repl-seq-mem-circuit=$(MODEL) \
diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml
index 27d290d2..2c529305 100644
--- a/conda-reqs/chipyard.yaml
+++ b/conda-reqs/chipyard.yaml
@@ -32,7 +32,7 @@ dependencies:
     - firtool>=1.29 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
 
     # firemarshal deps
-    - python>=3.8
+    - python>=3.9
     - bc
     - patch
     - which
@@ -122,6 +122,8 @@ dependencies:
     - boto3-stubs==1.21.6
     - botocore-stubs==1.24.7
     - mypy-boto3-s3==1.21.0
+    - sty==1.0.0
+    - sv2v
     - pip
     - pip:
         - fab-classic==1.19.1
diff --git a/vlsi/Makefile b/vlsi/Makefile
index 217f50e1..5ff80185 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -55,26 +55,6 @@ endif
 #########################################################################################
 # general rules
 #########################################################################################
-VLSI_RTL = $(build_dir)/syn.f
-
-.PHONY: custom_vlog gen_vlog
-
-custom_vlog: $(CUSTOM_VLOG)
-	echo "" > $(VLSI_RTL)
-	$(foreach file,$^,echo $file >> $(VLSI_RTL))
-
-gen_vlog: $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(TOP_SMEMS_FILE)
-	cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) > $(VLSI_RTL)
-	echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
-	echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
-
-
-ifneq ($(CUSTOM_VLOG), )
-$(VLSI_RTL): custom_vlog
-else
-$(VLSI_RTL): gen_vlog
-endif
-
 .PHONY: default
 default: all
 
@@ -85,6 +65,36 @@ all: drc lvs
 #########################################################################################
 include $(base_dir)/common.mk
 
+#########################################################################################
+# process RTL
+#########################################################################################
+VLSI_RTL = $(build_dir)/syn.f
+
+ifneq ($(CUSTOM_VLOG), )
+	RTL_DEPS = $(CUSTOM_VLOG)
+else
+	RTL_DEPS = $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) $(TOP_SMEMS_FILE)
+endif
+
+$(VLSI_RTL): $(RTL_DEPS)
+ifneq ($(CUSTOM_VLOG), )
+	> $(VLSI_RTL)
+	$(foreach file,$^,echo $(file) >> $(VLSI_RTL))
+else ifneq ($(CONVERT_SV2V), )
+	# Convert System Verilog to Verilog, uniquify, remove incompatible tasks
+	sv2v -w=adjacent --oversized-numbers \
+		-D=ASSERT_VERBOSE_COND=0 -D=STOP_COND=0 -D=PRINTF_COND=0 \
+		$(filter-out %.v,$(shell cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST)))
+	cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u | sed 's/.sv/.v/g' > $(VLSI_RTL)
+	cat $(VLSI_RTL) | xargs sed -i 's/\$$fwrite.*/;/g'
+	echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
+	echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
+else
+	cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u | > $(VLSI_RTL)
+	echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
+	echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
+endif
+
 #########################################################################################
 # srams
 #########################################################################################
diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk
index 6ce000a2..cc3f9d7e 100644
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -34,5 +34,7 @@ ifeq ($(tutorial),sky130-openroad)
     INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
     VLSI_OBJ_DIR      ?= build-sky130-openroad
     # This prevents multidimensional arrays (unsupported by Yosys) at the expense of elaboration time.
-    ENABLE_CUSTOM_FIRRTL_PASS = 1
+    #ENABLE_CUSTOM_FIRRTL_PASS = 1
+	# This runs sv2v for Yosys compatibility
+	CONVERT_SV2V = 1
 endif