Fix more bugs with arty100t
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@@ -62,6 +62,9 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
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val intSink = IntSinkNode(IntSinkPortSimple())
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intSink := intNexus :=* ibus.toPLIC
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// avoids a bug when there are no interrupt sources
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ibus.fromAsync := NullIntSource()
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// Need to have at least 1 driver to the tile notification sinks
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tileHaltXbarNode := IntSourceNode(IntSourcePortSimple())
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tileWFIXbarNode := IntSourceNode(IntSourcePortSimple())
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Submodule generators/testchipip updated: 653c86b0e8...0afbac5f02
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