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Fix more bugs with arty100t

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This commit is contained in:
Jerry Zhao
2023-02-14 17:15:44 -08:00
parent 85fa9d1120
commit 61cc18749a
7 changed files with 74 additions and 13 deletions
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13
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -24,13 +24,24 @@ class WithArty100TUARTTSI extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val ath = th.asInstanceOf[Arty100THarness]
val freq = p(PeripheryBusKey).dtsFrequency.get
val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
withClockAndReset(th.buildtopClock, th.buildtopReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
val uart_to_tsi = Module(new UARTToTSI(freq))
ram.module.io.tsi_ser.flipConnect(uart_to_tsi.io.serial)
th.asInstanceOf[Arty100THarness].io_uart_bb.bundle <> uart_to_tsi.io.uart
ath.io_uart_bb.bundle <> uart_to_tsi.io.uart
ath.other_leds(1) := uart_to_tsi.io.serial.out.valid
ath.other_leds(2) := uart_to_tsi.io.serial.in.valid
ath.other_leds(3) := uart_to_tsi.io.uart.rxd
ath.other_leds(4) := uart_to_tsi.io.uart.txd
ath.other_leds(9) := ram.module.io.adapter_state(0)
ath.other_leds(10) := ram.module.io.adapter_state(1)
ath.other_leds(11) := ram.module.io.adapter_state(2)
ath.other_leds(12) := ram.module.io.adapter_state(3)
}
})
}