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Fix more bugs with arty100t

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This commit is contained in:
Jerry Zhao
2023-02-14 17:15:44 -08:00
parent 85fa9d1120
commit 61cc18749a
7 changed files with 74 additions and 13 deletions
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39
fpga/src/main/scala/arty100t/Harness.scala
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@@ -1,7 +1,7 @@
package chipyard.fpga.arty100t
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode}
@@ -24,19 +24,20 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
val chiptop = LazyModule(p(BuildTop)(p))
val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
val harnessSysPLL = dp(PLLFactoryKey)()
val harnessSysPLL = dp(PLLFactoryKey)
val harnessSysPLLNode = harnessSysPLL()
println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
val dutWrangler = LazyModule(new ResetWrangler)
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLL
dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
harnessSysPLL := clockOverlay.overlayOutput.node
harnessSysPLLNode := clockOverlay.overlayOutput.node
val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL))
val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
val ddrInParams = chiptop match { case td: ChipTop =>
td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
lsys.memTLNode.edges.in(0)
@@ -45,11 +46,39 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
val ddrClient = TLClientNode(Seq(ddrInParams.master))
ddrOverlay.overlayOutput.ddr := ddrClient
val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput()))
val all_leds = ledOverlays.map(_.overlayOutput.led)
val status_leds = all_leds.take(3)
val other_leds = all_leds.drop(3)
def buildtopClock = dutClock.in.head._1.clock
def buildtopReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }
InModuleBody {
clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
// Blink the status LEDs for sanity
withClock(clk_100mhz) {
val period = (BigInt(100) << 20) / status_leds.size
val counter = RegInit(0.U(log2Ceil(period).W))
val on = RegInit(0.U(log2Ceil(status_leds.size).W))
status_leds.zipWithIndex.map { case (o,s) => o := on === s.U }
counter := Mux(counter === (period-1).U, 0.U, counter + 1.U)
when (counter === 0.U) {
on := Mux(on === (status_leds.size-1).U, 0.U, on + 1.U)
}
}
other_leds(0) := resetPin
harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
ddrOverlay.mig.module.clock := buildtopClock
ddrOverlay.mig.module.reset := buildtopReset
chiptop match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}