From 610adfc3f79fa01e28ab4899c6442228dbb3e397 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 3 Jun 2021 22:23:17 -0700 Subject: [PATCH] address PR review comments --- .../chipyard/src/main/scala/ConfigFragments.scala | 5 +++-- generators/firechip/src/main/scala/TargetConfigs.scala | 10 ++++++---- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 8bb455b4..0e07b038 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -325,11 +325,12 @@ class WithTestChipBusFreqs extends Config( new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540 new chipyard.config.WithSystemBusFrequency(800.0) ++ // Put the system bus at a lower freq, representative of ncore working at a lower frequency than the tiles. Same freq as U540 new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // 2x the U540 freq (appropriate for a 128b Mbus) - new chipyard.config.WithPeripheryBusFrequency(100) ++ // Match the sbus and pbus frequency + new chipyard.config.WithPeripheryBusFrequency(800.0) ++ // Match the sbus and pbus frequency new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (800 MHz) // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS - new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(4,4) ++ // Add Async crossings between RocketTile and uncore + new boom.common.WithAsynchronousBoomTiles ++ // Add Async crossings between BoomTile and uncore new testchipip.WithAsynchronousSerialSlaveCrossing // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d9e25a14..691ef15d 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -103,12 +103,14 @@ class WithFireSimHighPerfClocking extends Config( // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz class WithFireSimConfigTweaks extends Config( - // 1 GHz matches the FASED default, using some other frequency will require - // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values. - new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ - new chipyard.config.WithMemoryBusFrequency(1000.0) ++ + // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency) + // Using some other frequency will require runnings the FASED runtime configuration generator + // to generate faithful DDR3 timing values. new chipyard.config.WithSystemBusFrequency(1000.0) ++ new chipyard.config.WithSystemBusFrequencyAsDefault ++ // All unspecified clock frequencies, notably the implicit clock, will use the sbus freq (1000 MHz) + // Explicitly set PBUS + MBUS to 1000 MHz, since they will be driven to 100 MHz by default because of assignments in the Chisel + new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new WithFireSimDesignTweaks )