1st pass at connecting to harness PLL | Put UART adapter on harnessClock/Reset

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -21,7 +21,7 @@ import barstools.iocell.chisel._
 
 import testchipip._
 
-import chipyard.HasHarnessSignalReferences
+import chipyard.{HasHarnessSignalReferences, HarnessClockInstantiatorKey}
 import chipyard.iobinders.GetSystemParameters
 
 import tracegen.{TraceGenSystemModuleImp}
@@ -83,7 +83,9 @@ class WithGPIOTiedOff extends OverrideHarnessBinder({
 // DOC include start: WithUARTAdapter
 class WithUARTAdapter extends OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
-    UARTAdapter.connect(ports)(system.p)
+    withClockAndReset(th.harnessClock, th.harnessReset) {
+      UARTAdapter.connect(ports)(system.p)
+    }
   }
 })
 // DOC include end: WithUARTAdapter
@@ -140,7 +142,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({
 })
 
 class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
-  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[SerialAndPassthroughClockResetIO]) => {
+  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
 
     p(SerialTLKey).map({ sVal =>
@@ -148,26 +150,28 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
       require(sVal.axiMemOverSerialTLParams.isDefined)
       val axiDomainParams = sVal.axiMemOverSerialTLParams.get
 
-      val memFreq = axiDomainParams.axiClockParams match {
+      val memFreq: Double = axiDomainParams.axiClockParams match {
-        case Some(clkParams) => {
+        case Some(clkParams) => clkParams.clockFreqMHz * 1000000
-          BigInt(clkParams.clockFreqMHz.toInt)*1000000
-        }
         case None => {
-          // get freq. from what the master bus specifies
+          // get freq. from what the master of the serial link specifies
-          system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(p(SerialTLAttachKey).masterWhere).dtsFrequency.get
+          system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(p(SerialTLAttachKey).masterWhere).dtsFrequency.get.toDouble
         }
       }
 
       ports.map({ port =>
-        val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(system.serdesser.get, port, th.harnessReset)
+        val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
-        val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, port.clocked_serial.clock, th.harnessReset.asBool)
+          system.serdesser.get,
+          port,
+          p(HarnessClockInstantiatorKey).getClockBundleWire("mem_over_serial_tl_clock", memFreq),
+          th.harnessReset)
+        val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
         when (success) { th.success := true.B }
 
         // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
         (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
           val memSize = sVal.memParams.size
           val lineSize = p(CacheBlockBytes)
-          val mem = Module(new SimDRAM(memSize, lineSize, memFreq, edge.bundle)).suggestName("simdram")
+          val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toInt), edge.bundle)).suggestName("simdram")
           mem.io.axi <> axi_port.bits
           mem.io.clock := axi_port.clock
           mem.io.reset := axi_port.reset

generators/chipyard/src/main/scala/IOBinders.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.{SimAXIMem}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
 import freechips.rocketchip.util._
-import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters, ClockParameters, ClockGroup, ClockBundle, ClockBundleParameters}
+import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
 import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
 
 import sifive.blocks.devices.gpio._
@@ -260,49 +260,6 @@ class WithSerialTLIOCells extends OverrideIOBinder({
   }).getOrElse((Nil, Nil))
 })
 
-class WithSerialTLAndPassthroughClockPunchthrough extends OverrideLazyIOBinder({
-  (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ serial_io =>
-    implicit val p: Parameters = GetSystemParameters(system)
-
-    val sys = system.asInstanceOf[BaseSubsystem]
-
-    require(p(SerialTLKey).isDefined)
-    val sVal = p(SerialTLKey).get
-
-    // currently only the harness AXI port supports a passthrough clock
-    require(sVal.axiMemOverSerialTLParams.isDefined)
-    val axiDomainParams = sVal.axiMemOverSerialTLParams.get
-
-    val clockSinkNode = axiDomainParams.axiClockParams.map({ clkParams =>
-      // request clock to pass along
-      val node = ClockSinkNode(Seq(ClockSinkParameters(take = Some(ClockParameters(freqMHz = clkParams.clockFreqMHz)))))
-      (node
-        := ClockGroup()(p, ValName("mem_over_serialtl_domain"))
-        := sys.asyncClockGroupsNode)
-      node
-    })
-
-    def clockBundle = clockSinkNode match {
-      case Some(node) => node.in.head._1
-      case None => {
-        val dontCareClockBundle = new ClockBundle(ClockBundleParameters())
-        dontCareClockBundle.clock := DontCare
-        dontCareClockBundle.reset := DontCare
-        dontCareClockBundle
-      }
-    }
-
-    InModuleBody {
-      val port = IO(new SerialAndPassthroughClockResetIO(sVal.width)).suggestName(s"serial_tl_passthrough_clk")
-      port.clocked_serial <> serial_io
-      port.passthrough_clock_reset <> clockBundle
-
-      // return the ports and no IO cells
-      (Seq(port), Nil)
-    }
-  }).getOrElse(InModuleBody{(Nil, Nil)}).asInstanceOf[ModuleValue[IOBinderTuple]]
-})
-
 class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
   (system: CanHaveMasterAXI4MemPort) => {
     implicit val p: Parameters = GetSystemParameters(system)

generators/chipyard/src/main/scala/TestHarness.scala

@@ -57,6 +57,7 @@ class HarnessClockInstantiator {
       divider.io.clk_out
     }
 
+    // TODO: on the implicit clock just create a passthrough (don't instantiate a divider + reset catch)
     // connect wires to clock source
     for (sinkParams <- sinks) {
       val div = pllConfig.sinkDividerMap(sinkParams)

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -228,11 +228,7 @@ class MulticlockAXIOverSerialConfig extends Config(
   new testchipip.WithAsynchronousSerialSlaveCrossing ++
 
   new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
-  new chipyard.iobinders.WithSerialTLAndPassthroughClockPunchthrough ++ // add new clock for axi domain over serdes and passthrough ios
   new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
-  new testchipip.WithBlockDeviceLocations(
-    freechips.rocketchip.subsystem.PBUS,
-    freechips.rocketchip.subsystem.PBUS) ++ // put block device fully on PBUS to avoid clock crossings
 
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)