Unify multi-node btw chipyard/firechip | unify harness clocking

2023-05-12 08:21:18 -07:00
parent 0cbca54e19
commit 607c2b5a73
31 changed files with 441 additions and 634 deletions
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -17,8 +17,8 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}

 import testchipip.{SerialTLKey}

-import chipyard.{BuildSystem, ExtTLMem}
-import chipyard.harness.{DefaultClockFrequencyKey}
+import chipyard._
+import chipyard.harness._

 class WithDefaultPeripherals extends Config((site, here, up) => {
  case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
@@ -30,7 +30,7 @@ class WithSystemModifications extends Config((site, here, up) => {
  case DTSTimebase => BigInt((1e6).toLong)
  case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
    // invoke makefile for sdboot
-    val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong
+    val freqMHz = (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toLong
    val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin"
    require (make.! == 0, "Failed to build bootrom")
    p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
@@ -41,8 +41,14 @@ class WithSystemModifications extends Config((site, here, up) => {

 // DOC include start: AbstractVCU118 and Rocket
 class WithVCU118Tweaks extends Config(
-  // harness binders
+  // clocking
  new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
+  new chipyard.clocking.WithPassthroughClockGenerator ++
+  new chipyard.config.WithMemoryBusFrequency(100) ++
+  new chipyard.config.WithSystemBusFrequency(100) ++
+  new chipyard.config.WithPeripheryBusFrequency(100) ++
+  new WithFPGAFrequency(100) ++ // default 100MHz freq
+  // harness binders
  new WithUART ++
  new WithSPISDCard ++
  new WithDDRMem ++
@@ -55,8 +61,7 @@ class WithVCU118Tweaks extends Config(
  new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
  new chipyard.config.WithNoDebug ++ // remove debug module
  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
-  new WithFPGAFrequency(100) // default 100MHz freq
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
 )

 class RocketVCU118Config extends Config(
--- a/fpga/src/main/scala/vcu118/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala
@@ -9,12 +9,12 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
 import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}

-import chipyard.{CanHaveMasterTLMemPort}
-import chipyard.harness.{HasHarnessSignalReferences, OverrideHarnessBinder}
+import chipyard._
+import chipyard.harness._

 /*** UART ***/
 class WithUART extends OverrideHarnessBinder({
-  (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
+  (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
    th match { case vcu118th: VCU118FPGATestHarnessImp => {
      vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head
    } }
@@ -23,7 +23,7 @@ class WithUART extends OverrideHarnessBinder({

 /*** SPI ***/
 class WithSPISDCard extends OverrideHarnessBinder({
-  (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
+  (system: HasPeripherySPI, th: BaseModule with HasHarnessInstantiators, ports: Seq[SPIPortIO]) => {
    th match { case vcu118th: VCU118FPGATestHarnessImp => {
      vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head
    } }
@@ -32,7 +32,7 @@ class WithSPISDCard extends OverrideHarnessBinder({

 /*** Experimental DDR ***/
 class WithDDRMem extends OverrideHarnessBinder({
-  (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
+  (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => {
    th match { case vcu118th: VCU118FPGATestHarnessImp => {
      require(ports.size == 1)

--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -5,8 +5,9 @@ import chisel3.experimental.{IO}

 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}
-import freechips.rocketchip.tilelink.{TLClientNode}
-import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
+import freechips.rocketchip.subsystem.{SystemBusKey}

 import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
@@ -38,8 +39,6 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
  val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
  val ddr2       = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))

-  val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
-
 // DOC include start: ClockOverlay
  // place all clocks in the shell
  require(dp(ClockInputOverlayKey).size >= 1)
@@ -52,8 +51,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
  harnessSysPLL := sysClkNode

  // create and connect to the dutClock
-  println(s"VCU118 FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
-  val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
+  val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
+  val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
+  println(s"VCU118 FPGA Base Clock Freq: ${dutFreqMHz} MHz")
  val dutWrangler = LazyModule(new ResetWrangler)
  val dutGroup = ClockGroup()
  dutClock := dutWrangler.node := dutGroup := harnessSysPLL
@@ -80,19 +80,18 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
  val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL)).overlayOutput.ddr

  // connect 1 mem. channel to the FPGA DDR
-  val inParams = topDesign match { case td: ChipTop =>
-    td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
-      lsys.memTLNode.edges.in(0)
-    }
-  }
-  val ddrClient = TLClientNode(Seq(inParams.master))
+  val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
+    name = "chip_ddr",
+    sourceId = IdRange(0, 64)
+  )))))
  ddrNode := ddrClient

  // module implementation
  override lazy val module = new VCU118FPGATestHarnessImp(this)
 }

-class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
+class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+  require(p(MultiChipNChips) == 0)

  val vcu118Outer = _outer

@@ -119,25 +118,12 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
  val hReset = Wire(Reset())
  hReset := _outer.dutClock.in.head._1.reset

-  val buildtopClock = _outer.dutClock.in.head._1.clock
-  val buildtopReset = WireInit(hReset)
-  val dutReset = hReset.asAsyncReset
-  val success = false.B
+  def implicitClock = _outer.dutClock.in.head._1.clock
+  def implicitReset = hReset
+  def success = { require(false, "Unused"); false.B }

-  childClock := buildtopClock
-  childReset := buildtopReset
+  childClock := implicitClock
+  childReset := implicitReset

-  // harness binders are non-lazy
-  _outer.topDesign match { case d: HasIOBinders =>
-    ApplyHarnessBinders(this, d.lazySystem, d.portMap)
-  }
-
-  // check the top-level reference clock is equal to the default
-  // non-exhaustive since you need all ChipTop clocks to equal the default
-  require(getRefClockFreq == p(DefaultClockFrequencyKey))
-
-  val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
-  implicitHarnessClockBundle.clock := buildtopClock
-  implicitHarnessClockBundle.reset := buildtopReset
-  harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
+  instantiateChipTops()
 }
--- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
@@ -13,11 +13,11 @@ import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}

 import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}

-import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder, HasHarnessSignalReferences}
+import chipyard.harness._

 /*** UART ***/
 class WithBringupUART extends ComposeHarnessBinder({
-  (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
+  (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[UARTPortIO]) => {
    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
      require(ports.size == 2)

@@ -28,7 +28,7 @@ class WithBringupUART extends ComposeHarnessBinder({

 /*** I2C ***/
 class WithBringupI2C extends OverrideHarnessBinder({
-  (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
+  (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[I2CPort]) => {
    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
      require(ports.size == 1)

@@ -39,7 +39,7 @@ class WithBringupI2C extends OverrideHarnessBinder({

 /*** GPIO ***/
 class WithBringupGPIO extends OverrideHarnessBinder({
-  (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
+  (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessInstantiators, ports: Seq[GPIOPortIO]) => {
    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
      (vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
        bb_io.bundle <> dut_io
@@ -50,7 +50,7 @@ class WithBringupGPIO extends OverrideHarnessBinder({

 /*** TSI Host Widget ***/
 class WithBringupTSIHost extends OverrideHarnessBinder({
-  (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => {
+  (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessInstantiators, ports: Seq[Data]) => {
    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
      require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link

--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -1,5 +1,4 @@
 package chipyard.fpga.vcu118.bringup
-
 import chisel3._

 import freechips.rocketchip.diplomacy._
@@ -22,6 +21,7 @@ import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidget
 import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}

 import chipyard.{ChipTop}
+import chipyard.harness._

 class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness {

@@ -78,12 +78,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
  dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb))

  // connect 1 mem. channel to the FPGA DDR
-  val inTsiParams = topDesign match { case td: ChipTop =>
-    td.lazySystem match { case lsys: HasPeripheryTSIHostWidget =>
-      lsys.tsiMemTLNodes.head.edges.in(0)
-    }
-  }
-  val tsiDdrClient = TLClientNode(Seq(inTsiParams.master))
+  val tsiDdrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
+    name = "chip_ddr",
+    sourceId = IdRange(0, 64)
+  )))))
  (ddr2Node
    := TLFragmenter(8,64,holdFirstDeny=true)
    := TLCacheCork()