Unify multi-node btw chipyard/firechip | unify harness clocking

fpga/src/main/scala/vc707/Configs.scala

@@ -18,7 +18,7 @@ import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
 import testchipip.{SerialTLKey}
 
 import chipyard.{BuildSystem, ExtTLMem}
-import chipyard.harness.{DefaultClockFrequencyKey}
+import chipyard.harness._
 
 class WithDefaultPeripherals extends Config((site, here, up) => {
   case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
@@ -29,7 +29,7 @@ class WithSystemModifications extends Config((site, here, up) => {
   case DTSTimebase => BigInt{(1e6).toLong}
   case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
     // invoke makefile for sdboot
-    val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong
+    val freqMHz = (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toLong
     val make = s"make -C fpga/src/main/resources/vc707/sdboot PBUS_CLK=${freqMHz} bin"
     require (make.! == 0, "Failed to build bootrom")
     p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
@@ -39,6 +39,15 @@ class WithSystemModifications extends Config((site, here, up) => {
 })
 
 class WithVC707Tweaks extends Config (
+  // clocking
+  new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
+  new chipyard.clocking.WithPassthroughClockGenerator ++
+  new chipyard.config.WithMemoryBusFrequency(50.0) ++
+  new chipyard.config.WithSystemBusFrequency(50.0) ++
+  new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+
+  new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
+  new WithFPGAFrequency(50) ++ // default 50MHz freq
   // harness binders
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new WithVC707UARTHarnessBinder ++
@@ -54,8 +63,7 @@ class WithVC707Tweaks extends Config (
   new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
   new chipyard.config.WithNoDebug ++ // remove debug module
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
-  new WithFPGAFrequency(50) // default 50MHz freq
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
 )
 
 class RocketVC707Config extends Config (

fpga/src/main/scala/vc707/TestHarness.scala

@@ -1,25 +1,25 @@
 package chipyard.fpga.vc707
-
 import chisel3._
 import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
 import org.chipsalliance.cde.config.{Parameters}
-import freechips.rocketchip.tilelink.{TLClientNode}
-import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.subsystem.{SystemBusKey}
+import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
 
 import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
 import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
-import sifive.fpgashells.shell.{ClockInputOverlayKey, ClockInputDesignInput, UARTOverlayKey, UARTDesignInput, UARTShellInput, LEDOverlayKey, LEDDesignInput, SwitchOverlayKey, SwitchDesignInput, ButtonOverlayKey, ButtonDesignInput, SPIOverlayKey, SPIDesignInput, ChipLinkOverlayKey, ChipLinkDesignInput, PCIeOverlayKey, PCIeDesignInput, PCIeShellInput, DDROverlayKey, DDRDesignInput, JTAGDebugOverlayKey, JTAGDebugDesignInput}
+import sifive.fpgashells.shell._
 import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
 import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
 
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
 
-import chipyard.{ChipTop, ExtTLMem, CanHaveMasterTLMemPort}
+import chipyard._
 import chipyard.iobinders.{HasIOBinders}
-import chipyard.harness.{ApplyHarnessBinders, HasHarnessSignalReferences, BuildTop, DefaultClockFrequencyKey}
+import chipyard.harness._
 
 class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>
 
@@ -28,8 +28,6 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
   // Order matters; ddr depends on sys_clock
   val uart = Overlay(UARTOverlayKey, new UARTVC707ShellPlacer(this, UARTShellInput()))
 
-  val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
-
   // place all clocks in the shell
   require(dp(ClockInputOverlayKey).size >= 1)
   val sysClkNode = dp(ClockInputOverlayKey).head.place(ClockInputDesignInput()).overlayOutput.node
@@ -41,8 +39,9 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
   harnessSysPLL := sysClkNode
 
   // create and connect to the dutClock
-  println(s"VC707 FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
-  val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
+  val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
+  val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
+  println(s"VC707 FPGA Base Clock Freq: ${dutFreqMHz} MHz")
   val dutWrangler = LazyModule(new ResetWrangler)
   val dutGroup = ClockGroup()
   dutClock := dutWrangler.node := dutGroup := harnessSysPLL
@@ -77,21 +76,19 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
 
   // Modify the last field of `DDRDesignInput` for 1GB RAM size
   val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr
+  val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
+    name = "chip_ddr",
+    sourceId = IdRange(0, 64)
+  )))))
 
-  // connect 1 mem. channel to the FPGA DDR
-  val inParams = topDesign match { case td: ChipTop =>
-    td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
-      lsys.memTLNode.edges.in(0)
-    }
-  }
-  val ddrClient = TLClientNode(Seq(inParams.master))
   ddrNode := ddrClient
 
   // module implementation
   override lazy val module = new VC707FPGATestHarnessImp(this)
 }
 
-class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
+class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+  require (p(MultiChipNChips) == 0)
 
   val vc707Outer = _outer
 
@@ -117,25 +114,12 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
   val hReset = Wire(Reset())
   hReset := _outer.dutClock.in.head._1.reset
 
-  val buildtopClock = _outer.dutClock.in.head._1.clock
-  val buildtopReset = WireInit(hReset)
-  val dutReset = hReset.asAsyncReset
-  val success = false.B
+  def implicitClock = _outer.dutClock.in.head._1.clock
+  def implicitReset = hReset
+  def success = { require(false, "Unused"); false.B }
 
-  childClock := buildtopClock
-  childReset := buildtopReset
+  childClock := implicitClock
+  childReset := implicitReset
 
-  // harness binders are non-lazy
-  _outer.topDesign match { case d: HasIOBinders =>
-    ApplyHarnessBinders(this, d.lazySystem, d.portMap)
-  }
-
-  // check the top-level reference clock is equal to the default
-  // non-exhaustive since you need all ChipTop clocks to equal the default
-  require(getRefClockFreq == p(DefaultClockFrequencyKey))
-
-  val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
-  implicitHarnessClockBundle.clock := buildtopClock
-  implicitHarnessClockBundle.reset := buildtopReset
-  harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
+  instantiateChipTops()
 }