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Unify multi-node btw chipyard/firechip | unify harness clocking

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This commit is contained in:
Jerry Zhao
2023-05-12 08:21:18 -07:00
parent 0cbca54e19
commit 607c2b5a73
31 changed files with 441 additions and 634 deletions
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8
fpga/src/main/scala/arty100t/Configs.scala
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@@ -26,6 +26,12 @@ class WithArty100TTweaks extends Config(
new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++
new WithNoDesignKey ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
@@ -34,8 +40,6 @@ class WithArty100TTweaks extends Config(
class RocketArty100TConfig extends Config(
new WithArty100TTweaks ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.RocketConfig)

56
fpga/src/main/scala/arty100t/Harness.scala
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@@ -4,8 +4,9 @@ import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
import freechips.rocketchip.subsystem.{SystemBusKey}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.shell._
@@ -14,21 +15,21 @@ import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.blocks.devices.uart._
import chipyard.{ChipTop, CanHaveMasterTLMemPort, ExtTLMem}
import chipyard._
import chipyard.harness._
import chipyard.iobinders.{HasIOBinders}
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell with HasHarnessSignalReferences
{
class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
def dp = designParameters
val chiptop = LazyModule(p(BuildTop)(p))
require(dp(MultiChipNChips) == 0, "Arty100T harness does not support multi-chip")
val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
val harnessSysPLL = dp(PLLFactoryKey)
val harnessSysPLLNode = harnessSysPLL()
println(s"Arty100T FPGA Base Clock Freq: ${dp(DefaultClockFrequencyKey)} MHz")
val dutClock = ClockSinkNode(freqMHz = dp(DefaultClockFrequencyKey))
val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
println(s"Arty100T FPGA Base Clock Freq: ${dutFreqMHz} MHz")
val dutWrangler = LazyModule(new ResetWrangler())
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
@@ -39,12 +40,10 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
val ddrInParams = chiptop match { case td: ChipTop =>
td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
lsys.memTLNode.edges.in(0)
}
}
val ddrClient = TLClientNode(Seq(ddrInParams.master))
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
sourceId = IdRange(0, 64)
)))))
val ddrBlockDuringReset = LazyModule(new TLBlockDuringReset(4))
ddrOverlay.overlayOutput.ddr := ddrBlockDuringReset.node := ddrClient
@@ -53,17 +52,16 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
val status_leds = all_leds.take(3)
val other_leds = all_leds.drop(3)
def buildtopClock = dutClock.in.head._1.clock
def buildtopReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }
InModuleBody {
override lazy val module = new HarnessLikeImpl
class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
val clk_100mhz = clockOverlay.overlayOutput.node.out.head._1.clock
// Blink the status LEDs for sanity
withClock(clk_100mhz) {
withClockAndReset(clk_100mhz, dutClock.in.head._1.reset) {
val period = (BigInt(100) << 20) / status_leds.size
val counter = RegInit(0.U(log2Ceil(period).W))
val on = RegInit(0.U(log2Ceil(status_leds.size).W))
@@ -78,21 +76,17 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
ddrOverlay.mig.module.clock := buildtopClock
ddrOverlay.mig.module.reset := buildtopReset
ddrBlockDuringReset.module.clock := buildtopClock
ddrBlockDuringReset.module.reset := buildtopReset || !ddrOverlay.mig.module.io.port.init_calib_complete
def implicitClock = dutClock.in.head._1.clock
def implicitReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }
ddrOverlay.mig.module.clock := harnessBinderClock
ddrOverlay.mig.module.reset := harnessBinderReset
ddrBlockDuringReset.module.clock := harnessBinderClock
ddrBlockDuringReset.module.reset := harnessBinderReset.asBool || !ddrOverlay.mig.module.io.port.init_calib_complete
other_leds(6) := ddrOverlay.mig.module.io.port.init_calib_complete
chiptop match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
val implicitHarnessClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
implicitHarnessClockBundle.clock := buildtopClock
implicitHarnessClockBundle.reset := buildtopReset
harnessClockInstantiator.instantiateHarnessClocks(implicitHarnessClockBundle)
instantiateChipTops()
}
}

39
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -6,6 +6,7 @@ import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
import freechips.rocketchip.tilelink.{TLBundle}
import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
@@ -20,39 +21,37 @@ import chipyard.iobinders.JTAGChipIO
import testchipip._
class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
(system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val ath = th.asInstanceOf[Arty100THarness]
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val freq = p(PeripheryBusKey).dtsFrequency.get
val bits = port.bits
port.clock := th.buildtopClock
withClockAndReset(th.buildtopClock, th.buildtopReset) {
val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset)
val uart_to_serial = Module(new UARTToSerial(
freq, UARTParams(0, initBaudRate=uartBaudRate)))
val serial_width_adapter = Module(new SerialWidthAdapter(
narrowW = 8, wideW = TSI.WIDTH))
serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
port.clock := th.harnessBinderClock
val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
val uart_to_serial = Module(new UARTToSerial(
freq, UARTParams(0, initBaudRate=uartBaudRate)))
val serial_width_adapter = Module(new SerialWidthAdapter(
narrowW = 8, wideW = TSI.WIDTH))
serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
ath.io_uart_bb.bundle <> uart_to_serial.io.uart
ath.other_leds(1) := uart_to_serial.io.dropped
ath.io_uart_bb.bundle <> uart_to_serial.io.uart
ath.other_leds(1) := uart_to_serial.io.dropped
ath.other_leds(9) := ram.module.io.tsi2tl_state(0)
ath.other_leds(10) := ram.module.io.tsi2tl_state(1)
ath.other_leds(11) := ram.module.io.tsi2tl_state(2)
ath.other_leds(12) := ram.module.io.tsi2tl_state(3)
}
ath.other_leds(9) := ram.module.io.tsi2tl_state(0)
ath.other_leds(10) := ram.module.io.tsi2tl_state(1)
ath.other_leds(11) := ram.module.io.tsi2tl_state(2)
ath.other_leds(12) := ram.module.io.tsi2tl_state(3)
})
}
})
class WithArty100TDDRTL extends OverrideHarnessBinder({
(system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
(system: CanHaveMasterTLMemPort, th: HasHarnessInstantiators, ports: Seq[HeterogeneousBag[TLBundle]]) => {
require(ports.size == 1)
val artyTh = th.asInstanceOf[Arty100THarness]
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val bundles = artyTh.ddrClient.out.map(_._1)
val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }