Bump fpga-platforms to new organized testchipip
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@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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import sifive.fpgashells.shell.{DesignKey}
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import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
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import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
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import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
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import chipyard.{BuildSystem}
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