Bump fpga-platforms to new organized testchipip

2023-12-19 12:17:00 -08:00
parent 1e5ebf192a
commit 604cb6358f
17 changed files with 19 additions and 22 deletions
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}

-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}

 import chipyard.{BuildSystem, ExtTLMem}
 import chipyard.harness._