Bump fpga-platforms to new organized testchipip

2023-12-19 12:17:00 -08:00
parent 1e5ebf192a
commit 604cb6358f
17 changed files with 19 additions and 22 deletions
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -20,8 +20,6 @@ import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._

-import testchipip._
-
 class WithArty100TUARTTSI extends HarnessBinder({
  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]