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Bump fpga-platforms to new organized testchipip

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This commit is contained in:
Jerry Zhao
2023-12-19 12:17:00 -08:00
parent 1e5ebf192a
commit 604cb6358f
17 changed files with 19 additions and 22 deletions
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6
fpga/src/main/scala/arty100t/Configs.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import sifive.fpgashells.shell.{DesignKey}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
@@ -25,7 +25,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++
new WithNoDesignKey ++
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
@@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config(
class BringupArty100TConfig extends Config(
new WithArty100TSerialTLToGPIO ++
new WithArty100TTweaks(freqMHz = 50) ++
new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new chipyard.ChipBringupHostConfig)