diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index edae3ac9..1b9a8512 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -25,7 +25,7 @@ Processor Cores See :ref:`Generators/CVA6:CVA6 Core` for more information. **Ibex Core** - An in-order RISC-V core writeen in System Verilog. + An in-order 32 bit RISC-V core written in System Verilog. See :ref:`Generators/Ibex:Ibex Core` for more information. Accelerators diff --git a/docs/Generators/Ibex.rst b/docs/Generators/Ibex.rst index 2b958358..f437c1e4 100644 --- a/docs/Generators/Ibex.rst +++ b/docs/Generators/Ibex.rst @@ -1,14 +1,14 @@ Ibex Core ==================================== -`Ibex `__ is a parameterizable RV32 embedded core written in SystemVerilog, currently maintained by lowRISC. +`Ibex `__ is a parameterizable RV32IMC embedded core written in SystemVerilog, currently maintained by `lowRISC `__. The `Ibex core` is wrapped in an `Ibex tile` so it can be used with the `Rocket Chip SoC generator`. The core exposes a custom memory interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. .. Warning:: The Ibex mtvec register is 256 byte aligned. When writing/running tests, ensure that the trap vector is also 256 byte aligned. -.. Warning:: The Ibex reset vector is located at 0x80. +.. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80. While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available. -For more information, see the `GitHub repository `__. \ No newline at end of file +For more information, see the `GitHub repository for Ibex `__. \ No newline at end of file