Bump testchipip

2021-03-21 15:34:01 -07:00
parent 55263971bc
commit 5ffad327db
4 changed files with 4 additions and 3 deletions
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -95,7 +95,7 @@ class WithFireSimDefaultFrequencyTweaks extends Config(
  // runnings the FASED runtime configuration generator to generate faithful DDR3 timing values.
  new chipyard.config.WithMemoryBusFrequency(1000.0) ++
  new chipyard.config.WithAsynchrousMemoryBusCrossing ++
-  new testchipip.WithAsynchronousSerialSlaveCrossing ++
+  new testchipip.WithAsynchronousSerialSlaveCrossing
 )

 // Tweaks that are generally applied to all firesim configs