From 5fcae018256a5f9992ce95f514928b61a988c83b Mon Sep 17 00:00:00 2001
From: Colin Schmidt <colins@eecs.berkeley.edu>
Date: Wed, 19 Feb 2020 18:52:48 -0800
Subject: [PATCH] Fix width of zeros after #74

---
 macros/src/test/scala/CostFunction.scala     |  2 +-
 macros/src/test/scala/MultiPort.scala        | 10 +++----
 macros/src/test/scala/SimpleSplitDepth.scala | 10 +++----
 macros/src/test/scala/SimpleSplitWidth.scala |  6 ++---
 macros/src/test/scala/SpecificExamples.scala | 28 ++++++++++----------
 macros/src/test/scala/SynFlops.scala         | 10 +++----
 6 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/macros/src/test/scala/CostFunction.scala b/macros/src/test/scala/CostFunction.scala
index 35936ed1..b8a27f7f 100644
--- a/macros/src/test/scala/CostFunction.scala
+++ b/macros/src/test/scala/CostFunction.scala
@@ -99,7 +99,7 @@ circuit target_memory :
     mem_0_3.din <= bits(din, 127, 96)
     mem_0_3.write_en <= and(and(and(write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1"))
     node dout_0 = cat(dout_0_3, cat(dout_0_2, cat(dout_0_1, dout_0_0)))
-    dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0"))
+    dout <= mux(UInt<1>("h1"), dout_0, UInt<128>("h0"))
 
   extmodule SRAM_WIDTH_32 :
     input addr : UInt<10>
diff --git a/macros/src/test/scala/MultiPort.scala b/macros/src/test/scala/MultiPort.scala
index fdaae9f7..3899f835 100644
--- a/macros/src/test/scala/MultiPort.scala
+++ b/macros/src/test/scala/MultiPort.scala
@@ -111,8 +111,8 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim
     mem_0_3.portB_read_en <= and(portB_read_en, UInt<1>("h1"))
     mem_0_3.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 3, 3)), UInt<1>("h1"))
     node portB_dout_0 = cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0)))
-    portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0"))
-    portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0"))
+    portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<64>("h0"))
+    portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<64>("h0"))
 """
 
   compileExecuteAndTest(mem, lib, v, output)
@@ -215,7 +215,7 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS
     node portA_dout_0_3 = bits(mem_0_3.portA_dout, 15, 0)
     mem_0_3.portA_read_en <= and(portA_read_en, UInt<1>("h1"))
     node portA_dout_0 = cat(portA_dout_0_3, cat(portA_dout_0_2, cat(portA_dout_0_1, portA_dout_0_0)))
-    portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0"))
+    portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<64>("h0"))
 """
 
   compileExecuteAndTest(mem, lib, v, output)
@@ -384,8 +384,8 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera
     mem_0_7.portB_read_en <= and(portB_read_en, UInt<1>("h1"))
     mem_0_7.portB_write_en <= and(and(and(portB_write_en, UInt<1>("h1")), bits(portB_mask, 7, 7)), UInt<1>("h1"))
     node portB_dout_0 = cat(portB_dout_0_7, cat(portB_dout_0_6, cat(portB_dout_0_5, cat(portB_dout_0_4, cat(portB_dout_0_3, cat(portB_dout_0_2, cat(portB_dout_0_1, portB_dout_0_0)))))))
-    portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<1>("h0"))
-    portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<1>("h0"))
+    portA_dout <= mux(UInt<1>("h1"), portA_dout_0, UInt<64>("h0"))
+    portB_dout <= mux(UInt<1>("h1"), portB_dout_0, UInt<64>("h0"))
 """
 
   compileExecuteAndTest(mem, lib, v, output)
diff --git a/macros/src/test/scala/SimpleSplitDepth.scala b/macros/src/test/scala/SimpleSplitDepth.scala
index 8df8ec7e..e3560f9a 100644
--- a/macros/src/test/scala/SimpleSplitDepth.scala
+++ b/macros/src/test/scala/SimpleSplitDepth.scala
@@ -48,7 +48,7 @@ s"""
       }
       def generate_outer_dout_tree(i:Int, depthInstances: Int): String = {
         if (i > depthInstances - 1) {
-          "UInt<1>(\"h0\")"
+          s"""UInt<${libWidth}>("h0")"""
         } else {
           s"""mux(eq(${memPortPrefix}_addr_sel_reg, UInt<%d>("h%s")), ${memPortPrefix}_dout_%d, %s)""".format(
             selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, depthInstances)
@@ -59,7 +59,7 @@ s"""
       if (selectBits > 0) {
         output append generate_outer_dout_tree(0, depthInstances)
       } else {
-        output append s"""mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<1>("h0"))"""
+        output append s"""mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<${libWidth}>("h0"))"""
       }
 
       output.toString
@@ -287,7 +287,7 @@ circuit target_memory :
 
     mem_1_0.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), eq(outer_addr_sel, UInt<1>("h1")))
     node outer_dout_1 = outer_dout_1_0
-    outer_dout <= mux(eq(outer_addr_sel_reg, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel_reg, UInt<1>("h1")), outer_dout_1, UInt<1>("h0")))
+    outer_dout <= mux(eq(outer_addr_sel_reg, UInt<1>("h0")), outer_dout_0, mux(eq(outer_addr_sel_reg, UInt<1>("h1")), outer_dout_1, UInt<8>("h0")))
   extmodule awesome_lib_mem :
     input lib_addr : UInt<10>
     input lib_clk : Clock
@@ -378,7 +378,7 @@ circuit target_memory :
     mem_1_0.innerA_addr <= outerB_addr
     node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
     node outerB_dout_1 = outerB_dout_1_0
-    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
+    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0")))
 
   extmodule awesome_lib_mem :
     input innerA_addr : UInt<10>
@@ -542,7 +542,7 @@ circuit target_memory :
     mem_1_0.innerA_addr <= outerB_addr
     node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
     node outerB_dout_1 = outerB_dout_1_0
-    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
+    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0")))
 
   extmodule awesome_lib_mem :
     input innerA_addr : UInt<10>
diff --git a/macros/src/test/scala/SimpleSplitWidth.scala b/macros/src/test/scala/SimpleSplitWidth.scala
index 9cc10f9d..843eed49 100644
--- a/macros/src/test/scala/SimpleSplitWidth.scala
+++ b/macros/src/test/scala/SimpleSplitWidth.scala
@@ -63,7 +63,7 @@ s"""
 
       output append
 s"""
-    ${memPortPrefix}_dout <= mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<1>("h0"))
+    ${memPortPrefix}_dout <= mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<${memWidth}>("h0"))
 """
       output.toString
     }
@@ -438,7 +438,7 @@ class SplitWidth1024x32_readEnable_Lib extends MacroCompilerSpec with HasSRAMGen
     mem_0_3.lib_read_en <= and(and(not(outer_write_en), UInt<1>("h1")), UInt<1>("h1"))
     mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1"))
     node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0)))
-    outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))
+    outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<32>("h0"))
 """
 
   compileExecuteAndTest(mem, lib, v, output)
@@ -536,7 +536,7 @@ class SplitWidth1024x32_readEnable_LibMem extends MacroCompilerSpec with HasSRAM
     mem_0_3.lib_read_en <= and(outer_read_en, UInt<1>("h1"))
     mem_0_3.lib_write_en <= and(and(and(outer_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1"))
     node outer_dout_0 = cat(outer_dout_0_3, cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0)))
-    outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))
+    outer_dout <= mux(UInt<1>("h1"), outer_dout_0, UInt<32>("h0"))
 """
 
   compileExecuteAndTest(mem, lib, v, output)
diff --git a/macros/src/test/scala/SpecificExamples.scala b/macros/src/test/scala/SpecificExamples.scala
index 56f4500f..e41932bb 100644
--- a/macros/src/test/scala/SpecificExamples.scala
+++ b/macros/src/test/scala/SpecificExamples.scala
@@ -76,7 +76,7 @@ circuit cc_banks_0_ext :
     mem_0_0.ren <= and(and(not(RW0_wmode), RW0_en), UInt<1>("h1"))
     mem_0_0.wen <= and(and(and(RW0_wmode, RW0_en), UInt<1>("h1")), UInt<1>("h1"))
     node RW0_rdata_0 = RW0_rdata_0_0
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0"))
 
   extmodule fake_mem :
     input addr : UInt<12>
@@ -159,7 +159,7 @@ circuit cc_dir_ext :
     mem_0_1.mport <= not(cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), bits(RW0_wmask, 4, 4)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
     mem_0_1.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1"))
     node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<128>("h0"))
 
   extmodule fake_mem :
     input addr : UInt<9>
@@ -486,7 +486,7 @@ circuit smem_0_ext :
     mem_1_3.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<1>("h1"))))
     mem_1_3.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<1>("h1"))))
     node R0_data_1 = cat(R0_data_1_3, cat(R0_data_1_2, cat(R0_data_1_1, R0_data_1_0)))
-    R0_data <= mux(eq(R0_addr_sel_reg, UInt<1>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<1>("h1")), R0_data_1, UInt<1>("h0")))
+    R0_data <= mux(eq(R0_addr_sel_reg, UInt<1>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<1>("h1")), R0_data_1, UInt<88>("h0")))
 
 
   module _T_84_ext :
@@ -621,7 +621,7 @@ circuit smem_0_ext :
     mem_3_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), eq(R0_addr_sel, UInt<2>("h3"))))
     mem_3_1.CSB2 <= not(and(R0_en, eq(R0_addr_sel, UInt<2>("h3"))))
     node R0_data_3 = cat(R0_data_3_1, R0_data_3_0)
-    R0_data <= mux(eq(R0_addr_sel_reg, UInt<2>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<2>("h1")), R0_data_1, mux(eq(R0_addr_sel_reg, UInt<2>("h2")), R0_data_2, mux(eq(R0_addr_sel_reg, UInt<2>("h3")), R0_data_3, UInt<1>("h0")))))
+    R0_data <= mux(eq(R0_addr_sel_reg, UInt<2>("h0")), R0_data_0, mux(eq(R0_addr_sel_reg, UInt<2>("h1")), R0_data_1, mux(eq(R0_addr_sel_reg, UInt<2>("h2")), R0_data_2, mux(eq(R0_addr_sel_reg, UInt<2>("h3")), R0_data_3, UInt<64>("h0")))))
 
   extmodule my_sram_2rw_128x32 :
     input A1 : UInt<7>
@@ -684,7 +684,7 @@ circuit smem_0_ext :
     mem_0_3.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1")))
     mem_0_3.CSB <= not(and(RW0_en, UInt<1>("h1")))
     node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<80>("h0"))
 
   extmodule my_sram_1rw_64x32 :
     input A : UInt<6>
@@ -723,7 +723,7 @@ circuit smem_0_ext :
     mem_0_1.WEB <= not(and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1")))
     mem_0_1.CSB <= not(and(RW0_en, UInt<1>("h1")))
     node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0"))
 
   extmodule my_sram_1rw_512x32 :
     input A : UInt<9>
@@ -776,7 +776,7 @@ circuit smem_0_ext :
     mem_0_1.WEB2 <= not(and(and(UInt<1>("h0"), UInt<1>("h1")), UInt<1>("h1")))
     mem_0_1.CSB2 <= not(and(R0_en, UInt<1>("h1")))
     node R0_data_0 = cat(R0_data_0_1, R0_data_0_0)
-    R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
+    R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<40>("h0"))
 
   extmodule my_sram_2rw_32x22 :
     input A1 : UInt<5>
@@ -1063,7 +1063,7 @@ circuit smem_0_ext :
     mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1")))
     mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1")))
     node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))))))))))))))))))))))))))
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<32>("h0"))
 
   module smem_0_ext :
     input RW0_addr : UInt<6>
@@ -1331,7 +1331,7 @@ circuit smem_0_ext :
     mem_0_31.WEB <= not(and(and(RW0_wmode, bits(RW0_wmask, 31, 31)), UInt<1>("h1")))
     mem_0_31.CSB <= not(and(RW0_en, UInt<1>("h1")))
     node RW0_rdata_0 = cat(RW0_rdata_0_31, cat(RW0_rdata_0_30, cat(RW0_rdata_0_29, cat(RW0_rdata_0_28, cat(RW0_rdata_0_27, cat(RW0_rdata_0_26, cat(RW0_rdata_0_25, cat(RW0_rdata_0_24, cat(RW0_rdata_0_23, cat(RW0_rdata_0_22, cat(RW0_rdata_0_21, cat(RW0_rdata_0_20, cat(RW0_rdata_0_19, cat(RW0_rdata_0_18, cat(RW0_rdata_0_17, cat(RW0_rdata_0_16, cat(RW0_rdata_0_15, cat(RW0_rdata_0_14, cat(RW0_rdata_0_13, cat(RW0_rdata_0_12, cat(RW0_rdata_0_11, cat(RW0_rdata_0_10, cat(RW0_rdata_0_9, cat(RW0_rdata_0_8, cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))))))))))))))))))))))))))
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<32>("h0"))
 
   extmodule my_sram_1rw_64x8 :
     input A : UInt<6>
@@ -1375,7 +1375,7 @@ class SmallTagArrayTest extends MacroCompilerSpec with HasSRAMGenerator with Has
        |    mem_0_0.mask <= cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(UInt<1>("h0"), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), cat(bits(mask, 0, 0), bits(mask, 0, 0))))))))))))))))))))))))))))))))
        |    mem_0_0.write_en <= and(and(write_en, UInt<1>("h1")), UInt<1>("h1"))
        |    node dout_0 = dout_0_0
-       |    dout <= mux(UInt<1>("h1"), dout_0, UInt<1>("h0"))
+       |    dout <= mux(UInt<1>("h1"), dout_0, UInt<26>("h0"))
     """.stripMargin
 
   compileExecuteAndTest(mem, lib, v, output)
@@ -1573,7 +1573,7 @@ circuit T_2172_ext :
     mem_0_3.din <= bits(RW0_wdata, 79, 60)
     mem_0_3.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 3, 3)), UInt<1>("h1"))
     node RW0_rdata_0 = cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<80>("h0"))
 
   extmodule SRAM1RW64x32 :
     input addr : UInt<6>
@@ -1605,7 +1605,7 @@ circuit T_2172_ext :
     mem_0_1.din <= bits(RW0_wdata, 63, 32)
     mem_0_1.write_en <= and(and(RW0_wmode, UInt<1>("h1")), UInt<1>("h1"))
     node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0"))
 
   extmodule SRAM1RW512x32 :
     input addr : UInt<9>
@@ -1675,7 +1675,7 @@ circuit T_2172_ext :
     mem_0_7.din <= bits(RW0_wdata, 63, 56)
     mem_0_7.write_en <= and(and(RW0_wmode, bits(RW0_wmask, 7, 7)), UInt<1>("h1"))
     node RW0_rdata_0 = cat(RW0_rdata_0_7, cat(RW0_rdata_0_6, cat(RW0_rdata_0_5, cat(RW0_rdata_0_4, cat(RW0_rdata_0_3, cat(RW0_rdata_0_2, cat(RW0_rdata_0_1, RW0_rdata_0_0)))))))
-    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<64>("h0"))
 
   extmodule SRAM1RW512x8 :
     input addr : UInt<9>
@@ -1731,7 +1731,7 @@ circuit T_2172_ext :
     mem_0_3.portA_addr <= R0_addr
     node R0_data_0_3 = bits(mem_0_3.portA_dout, 21, 0)
     node R0_data_0 = cat(R0_data_0_3, cat(R0_data_0_2, cat(R0_data_0_1, R0_data_0_0)))
-    R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<1>("h0"))
+    R0_data <= mux(UInt<1>("h1"), R0_data_0, UInt<88>("h0"))
 
   extmodule SRAM2RW64x32 :
     input portA_addr : UInt<6>
diff --git a/macros/src/test/scala/SynFlops.scala b/macros/src/test/scala/SynFlops.scala
index 0723bb33..f12161a1 100644
--- a/macros/src/test/scala/SynFlops.scala
+++ b/macros/src/test/scala/SynFlops.scala
@@ -13,7 +13,7 @@ s"""
     mem_0_0.${libPortPrefix}_din <= bits(${libPortPrefix}_din, ${libWidth-1}, 0)
     mem_0_0.${libPortPrefix}_write_en <= and(and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1"))
     node ${libPortPrefix}_dout_0 = ${libPortPrefix}_dout_0_0
-    ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<1>("h0"))
+    ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<${libWidth}>("h0"))
 
   module split_${lib_name} :
     input ${libPortPrefix}_addr : UInt<${lib_addr_width}>
@@ -162,7 +162,7 @@ circuit target_memory :
     mem_1_0.innerA_addr <= outerB_addr
     node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
     node outerB_dout_1 = outerB_dout_1_0
-    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
+    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0")))
 """
 
   override def generateFooterPorts =
@@ -187,7 +187,7 @@ circuit target_memory :
     mem_0_0.innerA_addr <= innerA_addr
     node innerA_dout_0_0 = bits(mem_0_0.innerA_dout, 7, 0)
     node innerA_dout_0 = innerA_dout_0_0
-    innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<1>("h0"))
+    innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<8>("h0"))
 
   module split_awesome_lib_mem :
     input innerA_addr : UInt<10>
@@ -294,7 +294,7 @@ circuit target_memory :
     mem_1_0.innerA_addr <= outerB_addr
     node outerB_dout_1_0 = bits(mem_1_0.innerA_dout, 7, 0)
     node outerB_dout_1 = outerB_dout_1_0
-    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<1>("h0")))
+    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0")))
 """
 
   override def generateFooterPorts =
@@ -384,7 +384,7 @@ circuit target_memory :
     mem_0_7.innerA_addr <= innerA_addr
     node innerA_dout_0_7 = bits(mem_0_7.innerA_dout, 0, 0)
     node innerA_dout_0 = cat(innerA_dout_0_7, cat(innerA_dout_0_6, cat(innerA_dout_0_5, cat(innerA_dout_0_4, cat(innerA_dout_0_3, cat(innerA_dout_0_2, cat(innerA_dout_0_1, innerA_dout_0_0)))))))
-    innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<1>("h0"))
+    innerA_dout <= mux(UInt<1>("h1"), innerA_dout_0, UInt<8>("h0"))
 
 
   module split_awesome_lib_mem :