From 40c84faa557b05a8800fc4d89bd2a9b4b3f19db6 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 1 Jan 2024 17:14:30 -0800 Subject: [PATCH 1/6] ADD: organize abstract config into sections --- .../main/scala/config/AbstractConfig.scala | 100 ++++++++++++------ 1 file changed, 68 insertions(+), 32 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index cef46e04..9534ed23 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -11,6 +11,9 @@ import org.chipsalliance.cde.config.{Config} // -------------- class AbstractConfig extends Config( + // ================================== + // Set up TestHarness + // ================================== // The HarnessBinders control generation of hardware in the TestHarness new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled @@ -28,6 +31,9 @@ class AbstractConfig extends Config( new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz + // ================================== + // Set up I/O harness + // ================================== // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs new chipyard.iobinders.WithSerialTLIOCells ++ @@ -51,38 +57,68 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ - // By default, punch out IOs to the Harness - new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ - new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus - new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus - new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus - new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus - new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus - new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus - - new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address - new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address - new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface + // ================================== + // Set up Memory Devices + // ================================== + // External memory section + new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ testchipip.serdes.SerialTLParams( - client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits - width = 32 // serial-tilelink interface with 32 lanes + client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), /** serial-tilelink interface will master the FBUS, and support 4 idBits */ + width = 32 /** serial-tilelink interface with 32 lanes */ ) )) ++ - new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks - new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels - new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model - new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 - new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + + // Peripheral section + new chipyard.config.WithUART ++ /** add a UART */ + + // Core section + new chipyard.config.WithBootROM ++ /** use default bootrom */ + new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ + new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ + + // ================================== + // Set up tiles + // ================================== + // Debug settings + new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ + // TODO: add these fragments + // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ + // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ + + // Cache settings + new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ + + // Memory settings + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ + + // Core Settings + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ + + // ================================== + // Set up reset and clocking + // ================================== + new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */ + new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ + + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */ + new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */ + new chipyard.config.WithControlBusFrequency(500.0) ++ /** Default 500 MHz cbus */ + new chipyard.config.WithSystemBusFrequency(500.0) ++ /** Default 500 MHz sbus */ + new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */ + new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */ + new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */ + + new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */ + new chipyard.clocking.WithPassthroughClockGenerator ++ + + // ================================== + // Base Settings + // ================================== + new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS */ + new freechips.rocketchip.system.BaseConfig) /** "base" rocketchip system */ From 502149d95fd4c734e4531335c029525721617081 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 1 Jan 2024 17:50:14 -0800 Subject: [PATCH 2/6] Update AbstractConfig.scala --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 9534ed23..7fe20bb7 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -76,16 +76,15 @@ class AbstractConfig extends Config( new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ - // ================================== - // Set up tiles - // ================================== - // Debug settings + // Debug section new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ - // TODO: add these fragments // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ + // ================================== + // Set up tiles + // ================================== // Cache settings new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ From 28ac74d11b2fb18cb03b2205f5068c407210b59b Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 1 Jan 2024 20:07:37 -0800 Subject: [PATCH 3/6] REFACTOR: adjust sections according to new mapping --- .../main/scala/config/AbstractConfig.scala | 67 ++++++++++++------- 1 file changed, 43 insertions(+), 24 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 7fe20bb7..24527687 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -11,9 +11,9 @@ import org.chipsalliance.cde.config.{Config} // -------------- class AbstractConfig extends Config( - // ================================== + // ================================================ // Set up TestHarness - // ================================== + // ================================================ // The HarnessBinders control generation of hardware in the TestHarness new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled @@ -31,9 +31,9 @@ class AbstractConfig extends Config( new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz - // ================================== + // ================================================ // Set up I/O harness - // ================================== + // ================================================ // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs new chipyard.iobinders.WithSerialTLIOCells ++ @@ -57,9 +57,9 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ - // ================================== - // Set up Memory Devices - // ================================== + // ================================================ + // Set up External Memory and IO Devices + // ================================================ // External memory section new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ testchipip.serdes.SerialTLParams( @@ -68,39 +68,54 @@ class AbstractConfig extends Config( ) )) ++ - // Peripheral section + // MMIO device section new chipyard.config.WithUART ++ /** add a UART */ - // Core section - new chipyard.config.WithBootROM ++ /** use default bootrom */ - new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ - new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ - - // Debug section + // ================================================ + // Set up Debugging + // ================================================ + // JTAG new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ + + // Boot Select Pins + new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ + new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ + + // ================================================ + // Set up Interrupts + // ================================================ + // CLINT and PLIC related settings goes here + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ + + // ================================================ + // Set up Tiles + // ================================================ + // core settings goes here + + + // ================================================ + // Set up Memory system + // ================================================ + // On-chip memory section + new chipyard.config.WithBootROM ++ /** use default bootrom */ - // ================================== - // Set up tiles - // ================================== // Cache settings new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ - // Memory settings + // Memory Bus settings new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ - // Core Settings - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ - - // ================================== - // Set up reset and clocking - // ================================== + // ================================================ + // Set up power, reset and clocking + // ================================================ + // clocking new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */ new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ @@ -116,6 +131,10 @@ class AbstractConfig extends Config( new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */ new chipyard.clocking.WithPassthroughClockGenerator ++ + // reset + + // power + // ================================== // Base Settings // ================================== From 1718e11a52a80405751e16de0767e852afe1cc4d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 2 Jan 2024 10:15:07 -0800 Subject: [PATCH 4/6] Reorganize AbstractConfig further --- .../main/scala/config/AbstractConfig.scala | 94 ++++++++++--------- 1 file changed, 48 insertions(+), 46 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 34151f86..7d75206d 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -15,24 +15,24 @@ class AbstractConfig extends Config( // Set up TestHarness // ================================================ // The HarnessBinders control generation of hardware in the TestHarness - new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present - new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled - new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM - new chipyard.harness.WithSimJTAGDebug ++ // add SimJTAG if JTAG for debug exposed - new chipyard.harness.WithSimDMI ++ // add SimJTAG if DMI exposed - new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present - new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled - new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled - new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present - new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present - new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present - new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port - new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator - new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness - new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz + new chipyard.harness.WithUARTAdapter ++ /** add UART adapter to display UART on stdout, if uart is present */ + new chipyard.harness.WithBlackBoxSimMem ++ /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */ + new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */ + new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */ + new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */ + new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */ + new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */ + new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */ + new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */ + new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */ + new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */ + new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */ + new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */ + new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */ // ================================================ - // Set up I/O harness + // Set up I/O cells + punch I/Os in ChipTop // ================================================ // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs @@ -61,66 +61,71 @@ class AbstractConfig extends Config( // Set up External Memory and IO Devices // ================================================ // External memory section - new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ + new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ testchipip.serdes.SerialTLParams( client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), /** serial-tilelink interface will master the FBUS, and support 4 idBits */ - width = 32 /** serial-tilelink interface with 32 lanes */ + width = 32 /** serial-tilelink interface with 32 lanes */ ) )) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ + + // MMIO device section - new chipyard.config.WithUART ++ /** add a UART */ - + new chipyard.config.WithUART ++ /** add a UART */ + // ================================================ - // Set up Debugging + // Set up Debug/Bringup/Testing Features // ================================================ // JTAG - new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ - // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ - // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data word capacity */ new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ // Boot Select Pins new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ - + // ================================================ // Set up Interrupts // ================================================ // CLINT and PLIC related settings goes here new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ - + // ================================================ // Set up Tiles // ================================================ - // core settings goes here - + // tile-local settings goes here // ================================================ // Set up Memory system // ================================================ // On-chip memory section - new chipyard.config.WithBootROM ++ /** use default bootrom */ - new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */ + new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */ + new chipyard.config.WithBootROM ++ /** use default bootrom */ + new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */ size = 64 * 1024) ++ - - // Cache settings - new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ - - // Memory Bus settings - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ + + // Coherency settings + new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence*/ + + // Bus/interconnect settings new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ // ================================================ // Set up power, reset and clocking // ================================================ - // clocking + + // ChipTop clock IO/PLL/Divider/Mux settings + new chipyard.clocking.WithPassthroughClockGenerator ++ + + // DigitalTop-internal clocking settings new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */ - new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ + new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */ + Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), + Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */ new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */ @@ -129,10 +134,8 @@ class AbstractConfig extends Config( new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */ new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */ new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */ - new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */ - new chipyard.clocking.WithPassthroughClockGenerator ++ - + // reset // power @@ -140,6 +143,5 @@ class AbstractConfig extends Config( // ================================== // Base Settings // ================================== - new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS */ new freechips.rocketchip.system.BaseConfig /** "base" rocketchip system */ ) From b79590bb698a230c24e62ee320622ee36c3a7455 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Sat, 10 Feb 2024 22:38:59 -0800 Subject: [PATCH 5/6] REFACTOR: fix spacing --- .../src/main/scala/config/AbstractConfig.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 9b10458c..751915e2 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -31,6 +31,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */ new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */ + // ================================================ // Set up I/O cells + punch I/Os in ChipTop // ================================================ @@ -58,6 +59,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ + // ================================================ // Set up External Memory and IO Devices // ================================================ @@ -75,6 +77,7 @@ class AbstractConfig extends Config( // MMIO device section new chipyard.config.WithUART ++ /** add a UART */ + // ================================================ // Set up Debug/Bringup/Testing Features // ================================================ @@ -86,17 +89,20 @@ class AbstractConfig extends Config( new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ + // ================================================ // Set up Interrupts // ================================================ // CLINT and PLIC related settings goes here new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ + // ================================================ // Set up Tiles // ================================================ // tile-local settings goes here + // ================================================ // Set up Memory system // ================================================ @@ -107,11 +113,12 @@ class AbstractConfig extends Config( size = 64 * 1024) ++ // Coherency settings - new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence*/ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence */ // Bus/interconnect settings new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ + // ================================================ // Set up power, reset and clocking // ================================================ @@ -140,6 +147,7 @@ class AbstractConfig extends Config( // power + // ================================== // Base Settings // ================================== From 4642bffae7d0a384d03f937e764780a5eab8f4bd Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Sat, 10 Feb 2024 23:03:19 -0800 Subject: [PATCH 6/6] FIX: add missing chipid harness --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 751915e2..96d252f7 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -26,6 +26,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */ new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */ new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */ + new chipyard.harness.WithDriveChipIdPin ++ /** drive chip id pin from harness binder, if chip id pin is present */ new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */ new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */ new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */ @@ -147,7 +148,7 @@ class AbstractConfig extends Config( // power - + // ================================== // Base Settings // ==================================