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abejgonzalez
2019-10-07 22:48:47 -07:00
parent f11fe16890
commit 5c5985de38
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docs/Software/FireMarshal.rst
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.. _fire-marshal: .. _fire-marshal:
FireMarshal FireMarshal
================= =================
``software/firemarshal``
FireMarshal is a workload generation tool for RISC-V based systems. It FireMarshal is a workload generation tool for RISC-V based systems. It
currently only supports the FireSim FPGA-accelerated simulation platform. currently only supports the FireSim FPGA-accelerated simulation platform.

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docs/Tools/Barstools.rst
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Barstools Barstools
=============================== ===============================
Barstools is a collection of useful FIRRTL transformations and Compilers to help the build process. Barstools is a collection of useful FIRRTL transformations and compilers to help the build process.
Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more. Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more.

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docs/Tools/Chisel-Testers.rst
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Chisel Testers Chisel Testers
============================== ==============================
`Chisel testers <https://github.com/freechipsproject/chisel-testers>`__ is a library for writing tests for Chisel designs. `Chisel Testers <https://github.com/freechipsproject/chisel-testers>`__ is a library for writing tests for Chisel designs.
It provides a Scala API for interacting with a DUT. It provides a Scala API for interacting with a DUT.
It can use multiple backends, including :ref:`Treadle` and Verilator. It can use multiple backends, including things such as Treadle and Verilator.
See :ref:`Treadle and FIRRTL Interpreter` and :ref:`sw-rtl-sim-intro` for more information on these simulation methods.

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docs/VLSI/Building-A-Chip.rst
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Building A Chip Building A Chip
============================== ==============================
TODO .. Note:: Please refer to the other sections in VLSI for tools/flows on how to build a chip. This section will be filled in ASAP.