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Add MMC Device section to the DTS

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abejgonzalez
2020-10-13 16:18:00 -07:00
parent 8257775e96
commit 5bbd865447
3 changed files with 12 additions and 4 deletions
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2
.gitmodules vendored
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@@ -21,7 +21,7 @@
url = https://github.com/riscv-boom/riscv-boom.git url = https://github.com/riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"] [submodule "generators/sifive-blocks"]
path = generators/sifive-blocks path = generators/sifive-blocks
url = https://github.com/sifive/sifive-blocks.git url = https://github.com/abejgonzalez/sifive-blocks.git
[submodule "generators/hwacha"] [submodule "generators/hwacha"]
path = generators/hwacha path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git url = https://github.com/ucb-bar/hwacha.git

12
fpga/src/main/scala/vcu118/Platform.scala
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@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118
import chisel3._ import chisel3._
import chisel3.experimental.{Analog, IO, DataMirror} import chisel3.experimental.{Analog, IO, DataMirror}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyScope, InModuleBody, BundleBridgeSource, ValName} import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle} import freechips.rocketchip.tilelink.{TLBundle}
@@ -23,10 +23,18 @@ trait HasVCU118PlatformIO {
val io_tl_mem: HeterogeneousBag[TLBundle] val io_tl_mem: HeterogeneousBag[TLBundle]
} }
class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope { class VCU118Platform(override implicit val p: Parameters) extends LazyModule with LazyScope with BindingScope {
val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
// add MMC to the DTS
lazySystem match { case lsys: HasPeripherySPI =>
val mmcDev = new MMCDevice(lsys.tlspi.head.device, 1)
ResourceBinding {
Resource(mmcDev, "reg").bind(ResourceAddress(0))
}
}
override lazy val module = new VCU118PlatformModule(this) override lazy val module = new VCU118PlatformModule(this)
} }

2
generators/sifive-blocks

Submodule generators/sifive-blocks updated: c240e629e2...413e0a88a4