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[clocks] Emit frequency summary for divider-only PLL model

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This commit is contained in:
David Biancolin
2020-09-29 16:59:37 -07:00
parent a6ce850391
commit 5b414f5829
2 changed files with 10 additions and 10 deletions
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17
generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala
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@@ -5,6 +5,7 @@ import chisel3._
import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._ import freechips.rocketchip.prci._
import freechips.rocketchip.util.ElaborationArtefacts
import scala.collection.mutable import scala.collection.mutable
import scala.collection.immutable.ListMap import scala.collection.immutable.ListMap
@@ -25,21 +26,22 @@ object FrequencyUtils {
} }
} }
class SimplePllConfiguration(val sinks: Seq[ClockSinkParameters]) { class SimplePllConfiguration(pllName: String, val sinks: Seq[ClockSinkParameters]) {
val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz
val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*) val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*)
def prettyPrint(pllName: String) { private val preamble = s"""
val preamble = s"""
|${pllName} Frequency Summary |${pllName} Frequency Summary
| Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin | Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin
val outputSummaries = sinkDividerMap.map { case (sink, division) => private val outputSummaries = sinkDividerMap.map { case (sink, division) =>
val requested = sink.take.get.freqMHz val requested = sink.take.get.freqMHz
val actual = referenceFreqMHz / division.toDouble val actual = referenceFreqMHz / division.toDouble
s" Output clock ${sink.name.get}, requested: ${requested} MHz, actual: ${actual} MHz (division of ${division})" s" Output clock ${sink.name.get}, requested: ${requested} MHz, actual: ${actual} MHz (division of ${division})"
} }
println(preamble + outputSummaries.mkString("\n"))
} val summaryString = preamble + outputSummaries.mkString("\n")
ElaborationArtefacts.add(s"${pllName}.freq-summary", summaryString)
println(summaryString)
} }
case class IdealizedPLLNode(pllName: String)(implicit valName: ValName) case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
@@ -71,8 +73,7 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex
val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head val (outClocks, ClockGroupEdgeParameters(_, outSinkParams, _, _)) = node.out.head
val referenceFreq = refSinkParam.take.get.freqMHz val referenceFreq = refSinkParam.take.get.freqMHz
val pllConfig = new SimplePllConfiguration(outSinkParams.members) val pllConfig = new SimplePllConfiguration(pllName, outSinkParams.members)
pllConfig.prettyPrint(pllName)
val dividedClocks = mutable.HashMap[Int, Clock]() val dividedClocks = mutable.HashMap[Int, Clock]()
def instantiateDivider(div: Int): Clock = { def instantiateDivider(div: Int): Clock = {

3
generators/firechip/src/main/scala/FireSim.scala
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@@ -124,8 +124,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => {
} }
} }
val pllConfig = new SimplePllConfiguration(clockGroupEdge.sink.members) val pllConfig = new SimplePllConfiguration("FireSim RationalClockBridge", clockGroupEdge.sink.members)
pllConfig.prettyPrint("FireSim RationalClockBridge")
val rationalClockSpecs = for ((sinkP, division) <- pllConfig.sinkDividerMap) yield { val rationalClockSpecs = for ((sinkP, division) <- pllConfig.sinkDividerMap) yield {
RationalClock(sinkP.name.get, 1, division) RationalClock(sinkP.name.get, 1, division)
} }