[clocks] Emit frequency summary for divider-only PLL model

2020-09-29 16:59:37 -07:00
parent a6ce850391
commit 5b414f5829
2 changed files with 10 additions and 10 deletions
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -124,8 +124,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => {
        }
      }

-      val pllConfig = new SimplePllConfiguration(clockGroupEdge.sink.members)
-      pllConfig.prettyPrint("FireSim RationalClockBridge")
+      val pllConfig = new SimplePllConfiguration("FireSim RationalClockBridge", clockGroupEdge.sink.members)
      val rationalClockSpecs = for ((sinkP, division) <- pllConfig.sinkDividerMap) yield {
        RationalClock(sinkP.name.get, 1, division)
      }