diff --git a/vlsi/.gitignore b/vlsi/.gitignore
index 4cbcfe8f..abe3347f 100644
--- a/vlsi/.gitignore
+++ b/vlsi/.gitignore
@@ -3,4 +3,5 @@ __pycache__
 hammer*.log
 build
 src/test/output-*.json
-generated-src
\ No newline at end of file
+generated-src
+output.json
diff --git a/vlsi/Makefile b/vlsi/Makefile
index 42af7ba2..912eecdd 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -19,18 +19,22 @@ include $(base_dir)/variables.mk
 #########################################################################################
 sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
 tech_name          ?= asap7
-tech_dir           ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
+tech_dir           ?= $(if $(filter $(tech_name),asap7 nangate45),\
+												$(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \
+												$(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
 SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
 SMEMS_HAMMER       ?= $(build_dir)/$(long_name).mems.hammer.json
-ifeq ($(tech_name),asap7)
-	MACROCOMPILER_MODE ?= --mode synflops
-else
-	MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
-endif
+MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\
+												--mode synflops,\
+												-l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict)
 ENV_YML            ?= $(vlsi_dir)/env.yml
-INPUT_CONFS        ?= example.yml
-HAMMER_EXEC        ?= ./example-vlsi
+INPUT_CONFS        ?= $(if $(filter $(tech_name),nangate45),\
+												example-nangate45.yml,\
+												example.yml)
+HAMMER_EXEC        ?= $(if $(filter $(tech_name),nangate45),\
+												example-vlsi-nangate45,\
+												example-vlsi)
 VLSI_TOP           ?= $(TOP)
 VLSI_HARNESS_DUT_NAME ?= dut
 VLSI_OBJ_DIR       ?= $(vlsi_dir)/build
diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml
new file mode 100644
index 00000000..de4d912f
--- /dev/null
+++ b/vlsi/example-nangate45.yml
@@ -0,0 +1,144 @@
+# Technology Setup
+# Technology used is nanagate45
+vlsi.core.technology: nangate45
+# Specify dir with ASAP7 tarball
+technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD"
+
+vlsi.core.max_threads: 12
+
+# General Hammer Inputs
+
+# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
+vlsi.inputs.power_spec_mode: "auto"
+vlsi.inputs.power_spec_type: "cpf"
+
+# Specify clock signals
+vlsi.inputs.clocks: [
+  {name: "clock", period: "5ns", uncertainty: "0.5ns"}
+]
+
+# Generate Make include to aid in flow 
+vlsi.core.build_system: make
+
+# Power Straps
+#par.power_straps_mode: generate
+#par.generate_power_straps_method: by_tracks
+#par.blockage_spacing: 2.0
+#par.generate_power_straps_options:
+#  by_tracks:
+#    strap_layers:
+#      - metal3
+#      - metal4
+#      - metal5
+#      - metal6
+#      - metal7
+#      - metal8
+#    pin_layers:
+#      - metal7
+#      - metal8
+#    track_width: 7 # minimum allowed for M2 & M3
+#    track_spacing: 0
+#    track_spacing_M3: 1 # to avoid M2 shorts at higher density
+#    track_start: 10
+#    power_utilization: 0.05
+#    power_utilization_M8: 1.0
+#    power_utilization_M9: 1.0
+
+# Placement Constraints
+# For ASAP7, all numbers must be 4x larger than final GDS
+vlsi.inputs.placement_constraints:
+  - path: "ChipTop"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 1387.38 
+    height: 1199.1
+    margins: 
+      left: 0
+      right: 0
+      top: 0
+      bottom: 0
+#  - path: "Sha3AccelwBB/dco"
+#    type: hardmacro
+#    x: 108
+#    y: 108
+#    width: 128
+#    height: 128
+#    orientation: r0
+#    top_layer: M9
+#  - path: "Sha3AccelwBB/place_obs_bottom"
+#    type: obstruction
+#    obs_types: ["place"]
+#    x: 0
+#    y: 0
+#    width: 300
+#    height: 1.08 # 1 core site tall, necessary to avoid shorts
+
+# Pin placement constraints
+#vlsi.inputs.pin_mode: generated
+#vlsi.inputs.pin.generate_mode: semi_auto
+#vlsi.inputs.pin.assignments: [
+#  {pins: "*", layers: ["metal7", "metal8"]}
+#]
+
+# Paths to extra libraries
+#vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
+#vlsi.technology.extra_libraries:
+#  - library:
+#      nldm liberty file_deepsubst_meta: "local"
+#      nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"
+#      lef file_deepsubst_meta: "local"
+#      lef file: "extra_libraries/example/ExampleDCO.lef"
+#      gds file_deepsubst_meta: "local"
+#      gds file: "extra_libraries/example/ExampleDCO.gds"
+#      corner:
+#        nmos: "slow"
+#        pmos: "slow"
+#        temperature: "100 C"
+#      supplies:
+#        VDD: "0.63 V"
+#        GND: "0 V"
+#  - library:
+#      nldm liberty file_deepsubst_meta: "local"
+#      nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"
+#      lef file_deepsubst_meta: "local"
+#      lef file: "extra_libraries/example/ExampleDCO.lef"
+#      gds file_deepsubst_meta: "local"
+#      gds file: "extra_libraries/example/ExampleDCO.gds"
+#      corner:
+#        nmos: "fast"
+#        pmos: "fast"
+#        temperature: "0 C"
+#      supplies:
+#        VDD: "0.77 V"
+#        GND: "0 V"
+
+# Because the DCO is a dummy layout, we treat it as a physical-only cell
+#par.inputs.physical_only_cells_mode: append
+#par.inputs.physical_only_cells_list:
+#  - ExampleDCO
+
+# SRAM Compiler compiler options
+vlsi.core.sram_generator_tool: "sram_compiler"
+## You should specify a location for the SRAM generator in the tech plugin
+vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/nangate45"]
+vlsi.core.sram_generator_tool_path_meta: "append"
+
+# Tool options. Replace with your tool plugin of choice.
+# yosys options
+vlsi.core.synthesis_tool: "yosys"
+vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"]
+vlsi.core.synthesis_tool_path_meta: "append"
+
+# Innovus options
+#vlsi.core.par_tool: "innovus"
+#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
+#vlsi.core.par_tool_path_meta: "append"
+#par.innovus.version: "181"
+#par.innovus.design_flow_effort: "standard"
+#par.inputs.gds_merge: true
+## Calibre options
+#vlsi.core.drc_tool: "calibre"
+#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
+#vlsi.core.lvs_tool: "calibre"
+#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
diff --git a/vlsi/example-vlsi-nangate45 b/vlsi/example-vlsi-nangate45
new file mode 100755
index 00000000..39b9a493
--- /dev/null
+++ b/vlsi/example-vlsi-nangate45
@@ -0,0 +1,29 @@
+#!/usr/bin/env python3
+import os
+
+import hammer_vlsi
+from hammer_vlsi import CLIDriver, HammerToolHookAction
+
+from typing import Dict, Callable, Optional, List
+
+def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
+    x.append("")
+    return True
+
+def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
+    x.append("")
+    return True
+
+class ExampleDriver(CLIDriver):
+    def get_extra_par_hooks(self) -> List[HammerToolHookAction]:
+        extra_hooks = [
+            # make_pre_insertion_hook will execute the custom hook before the specified step
+            hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
+
+            # make_replacement_hook will replace the specified step with a custom hook
+            hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
+        ]
+        return extra_hooks 
+
+if __name__ == '__main__':
+    ExampleDriver().main()
diff --git a/vlsi/hammer b/vlsi/hammer
index bd94e1ed..657feaed 160000
--- a/vlsi/hammer
+++ b/vlsi/hammer
@@ -1 +1 @@
-Subproject commit bd94e1ed7a5f70fe85ea833cb89836efefe53dc7
+Subproject commit 657feaed58014f4ef5b76acaa1e0cc559f182bda