From 5a885fdcfd621fffe6b1ad7c9a92d0dbbdf5db9c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 3 Sep 2020 21:28:05 -0700 Subject: [PATCH] Delete old makefiles | Full switch to CY make system --- fpga/.gitignore | 3 + fpga/Makefile | 73 +++++++---- fpga/Makefile.e300artydevkit | 23 ---- fpga/bootrom/xip/Makefile | 13 +- fpga/common.mk | 119 ------------------ .../utilities/src/main/scala/Simulator.scala | 50 ++++---- 6 files changed, 93 insertions(+), 188 deletions(-) create mode 100644 fpga/.gitignore delete mode 100644 fpga/Makefile.e300artydevkit delete mode 100644 fpga/common.mk diff --git a/fpga/.gitignore b/fpga/.gitignore new file mode 100644 index 00000000..a0991ff4 --- /dev/null +++ b/fpga/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!Makefile diff --git a/fpga/Makefile b/fpga/Makefile index dcafb930..837902bc 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -8,27 +8,35 @@ base_dir=$(abspath ..) sim_dir=$(abspath .) +# do not generate simulation files +sim_name := none + ######################################################################################### # include shared variables ######################################################################################### include $(base_dir)/variables.mk -export SUB_PROJECT=fpga -export SBT_PROJECT=freedomPlatforms -export MODEL=E300ArtyDevKitFPGAChip -export VLOG_MODEL=E300ArtyDevKitFPGAChip -export MODEL_PACKAGE=sifive.freedom.everywhere.e300artydevkit -export CONFIG=E300ArtyDevKitConfig -export CONFIG_PACKAGE=sifive.freedom.everywhere.e300artydevkit -export GENERATOR_PACKAGE=chipyard -export TB=none -export TOP=E300ArtyDevKitPlatform -export BOARD=arty +# default variables to build the arty example +SUB_PROJECT := fpga +SBT_PROJECT := freedomPlatforms +MODEL := E300ArtyDevKitFPGAChip +VLOG_MODEL := E300ArtyDevKitFPGAChip +MODEL_PACKAGE := sifive.freedom.everywhere.e300artydevkit +CONFIG := E300ArtyDevKitConfig +CONFIG_PACKAGE := sifive.freedom.everywhere.e300artydevkit +GENERATOR_PACKAGE := chipyard +TB := none # unused +TOP := E300ArtyDevKitPlatform -export bootrom_dir := $(base_dir)/fpga/bootrom/xip -fpga_dir=$(base_dir)/fpga/fpga-shells/xilinx +# setup the board to use +BOARD ?= arty -sim_name = verilator # unused +######################################################################################### +# misc. directories +######################################################################################### +bootrom_dir := $(base_dir)/fpga/bootrom/xip +fpga_common_script_dir := $(FPGA_DIR)/common/tcl +fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx ######################################################################################### # import other necessary rules and variables @@ -38,8 +46,23 @@ include $(base_dir)/common.mk ######################################################################################### # copy from other directory ######################################################################################### -romgen := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).rom.v -$(romgen): $(verilog) +all_vsrcs := \ + $(sim_vsrcs) \ + $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ + $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v \ + $(build_dir)/$(long_name).rom.v + +######################################################################################### +# build rom for the fpga +######################################################################################### +# needed for bootrom makefile +export BUILD_DIR=$(build_dir) +export ROCKETCHIP_DIR +export LONG_NAME=$(long_name) +export ROMCONF=$(build_dir)/$(long_name).rom.conf + +romgen := $(build_dir)/$(long_name).rom.v +$(romgen): $(sim_vsrcs) ifneq ($(bootrom_dir),"") $(MAKE) -C $(bootrom_dir) romgen mv $(build_dir)/rom.v $@ @@ -48,9 +71,14 @@ endif .PHONY: romgen romgen: $(romgen) -f := $(build_dir)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F -$(f): - echo $(VSRCS) > $@ +######################################################################################### +# vivado rules +######################################################################################### +# combine all sources into single .F +f := $(build_dir)/$(long_name).vsrcs.F +$(f): $(sim_common_files) $(all_vsrcs) + $(foreach file,$(all_vsrcs),echo "$(file)" >> $@;) + cat $(sim_common_files) >> $@ bit := $(build_dir)/obj/$(MODEL).bit $(bit): $(romgen) $(f) @@ -63,6 +91,8 @@ $(bit): $(romgen) $(f) -ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \ -board "$(BOARD)" +.PHONY: bit +bit: $(bit) # Build .mcs mcs := $(build_dir)/obj/$(MODEL).mcs @@ -72,6 +102,9 @@ $(mcs): $(bit) .PHONY: mcs mcs: $(mcs) +######################################################################################### +# mircosemi rules +######################################################################################### # Build Libero project prjx := $(build_dir)/libero/$(MODEL).prjx $(prjx): $(verilog) @@ -80,7 +113,6 @@ $(prjx): $(verilog) .PHONY: prjx prjx: $(prjx) - ######################################################################################### # general cleanup rules ######################################################################################### @@ -90,4 +122,3 @@ clean: ifneq ($(bootrom_dir),"") $(MAKE) -C $(bootrom_dir) clean endif - $(MAKE) -C $(FPGA_DIR) clean diff --git a/fpga/Makefile.e300artydevkit b/fpga/Makefile.e300artydevkit deleted file mode 100644 index 5f5c595b..00000000 --- a/fpga/Makefile.e300artydevkit +++ /dev/null @@ -1,23 +0,0 @@ -# See LICENSE for license details. -base_dir=$(abspath ..) -BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit -FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx -MODEL := E300ArtyDevKitFPGAChip -PROJECT := sifive.freedom.everywhere.e300artydevkit -export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit -export CONFIG := E300ArtyDevKitConfig -export BOARD := arty -export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip - -rocketchip_dir := $(base_dir)/generators/rocket-chip -sifiveblocks_dir := $(base_dir)/generators/sifive-blocks -VSRCS := \ - $(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \ - $(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \ - $(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \ - $(sifiveblocks_dir)/vsrc/SRLatch.v \ - $(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \ - $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \ - $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v - -include common.mk diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile index 57f94d49..e51fd9c5 100644 --- a/fpga/bootrom/xip/Makefile +++ b/fpga/bootrom/xip/Makefile @@ -1,12 +1,17 @@ # RISCV environment variable must be set +# needs the following variables +# LONG_NAME +# BUILD_DIR +# ROCKETCHIP_DIR +# ROMCONF CC=$(RISCV)/bin/riscv64-unknown-elf-gcc OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g LFLAGS=-static -nostdlib -dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb -$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts +dtb := $(BUILD_DIR)/$(LONG_NAME).dtb +$(dtb): $(BUILD_DIR)/$(LONG_NAME).dts dtc -I dts -O dtb -o $@ $< .PHONY: dtb @@ -35,11 +40,11 @@ hex: $(hex) romgen := $(BUILD_DIR)/rom.v $(romgen): $(hex) - $(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ + $(ROCKETCHIP_DIR)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@ .PHONY: romgen romgen: $(romgen) .PHONY: clean clean:: - rm -rf $(hex) $(elf) + rm -rf $(hex) $(elf) diff --git a/fpga/common.mk b/fpga/common.mk deleted file mode 100644 index 5466ed7b..00000000 --- a/fpga/common.mk +++ /dev/null @@ -1,119 +0,0 @@ -# See LICENSE for license details. - -# Required variables: -# - MODEL -# - PROJECT -# - CONFIG_PROJECT -# - CONFIG -# - BUILD_DIR -# - FPGA_DIR - -# Optional variables: -# - EXTRA_FPGA_VSRCS - -# export to bootloader -export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf - -# export to fpga-shells -export FPGA_TOP_SYSTEM=$(MODEL) -export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM) -export fpga_common_script_dir=$(FPGA_DIR)/common/tcl -export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl - -export BUILD_DIR - -EXTRA_FPGA_VSRCS ?= -PATCHVERILOG ?= "" -BOOTROM_DIR ?= "" - -base_dir=$(abspath ..) -export rocketchip_dir := $(base_dir)/generators/rocket-chip -SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10 -SBT_PROJECT ?= chipyard -firrtl_dir := $(base_dir)/tools/firrtl - -# Build firrtl.jar and put it where chisel3 can find it. -FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver - -$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala") - $(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala - mkdir -p $(base_dir)/lib - cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR) - -# Build .fir -long_name := $(CONFIG_PROJECT).$(CONFIG) -firrtl := $(BUILD_DIR)/$(long_name).fir -$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR) - mkdir -p $(dir $@) - cd $(base_dir) && $(SBT) "project freedomPlatforms" \ - "runMain chipyard.Generator \ - --target-dir $(BUILD_DIR) \ - --name $(long_name) \ - --top-module $(PROJECT).$(MODEL) \ - --legacy-configs $(CONFIG_PROJECT).$(CONFIG)" - -.PHONY: firrtl -firrtl: $(firrtl) - -# Build .v -verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v -$(verilog): $(firrtl) $(FIRRTL_JAR) - $(FIRRTL) -i $(firrtl) -o $@ -X verilog -ifneq ($(PATCHVERILOG),"") - $(PATCHVERILOG) -endif - -.PHONY: verilog -verilog: $(verilog) - -romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v -$(romgen): $(verilog) -ifneq ($(BOOTROM_DIR),"") - $(MAKE) -C $(BOOTROM_DIR) romgen - mv $(BUILD_DIR)/rom.v $@ -endif - -.PHONY: romgen -romgen: $(romgen) - -f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F -$(f): - echo $(VSRCS) > $@ - -bit := $(BUILD_DIR)/obj/$(MODEL).bit -$(bit): $(romgen) $(f) - cd $(BUILD_DIR); vivado \ - -nojournal -mode batch \ - -source $(fpga_common_script_dir)/vivado.tcl \ - -tclargs \ - -top-module "$(MODEL)" \ - -F "$(f)" \ - -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \ - -board "$(BOARD)" - - -# Build .mcs -mcs := $(BUILD_DIR)/obj/$(MODEL).mcs -$(mcs): $(bit) - cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $< - -.PHONY: mcs -mcs: $(mcs) - -# Build Libero project -prjx := $(BUILD_DIR)/libero/$(MODEL).prjx -$(prjx): $(verilog) - cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)" - -.PHONY: prjx -prjx: $(prjx) - -# Clean -.PHONY: clean -clean: -ifneq ($(BOOTROM_DIR),"") - $(MAKE) -C $(BOOTROM_DIR) clean -endif - $(MAKE) -C $(FPGA_DIR) clean - rm -rf $(BUILD_DIR) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index b2982db7..43edd33a 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -11,6 +11,7 @@ case class GenerateSimConfig( sealed trait Simulator object VerilatorSimulator extends Simulator object VCSSimulator extends Simulator +object NotSimulator extends Simulator trait HasGenerateSimConfig { val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") { @@ -22,15 +23,16 @@ trait HasGenerateSimConfig { .action((x, c) => x match { case "verilator" => c.copy(simulator = VerilatorSimulator) case "vcs" => c.copy(simulator = VCSSimulator) + case "none" => c.copy(simulator = NotSimulator) case _ => throw new Exception(s"Unrecognized simulator $x") }) - .text("Name of simulator to generate files for (verilator, vcs)") + .text("Name of simulator to generate files for (verilator, vcs, none)") opt[String]("target-dir") .abbr("td") .valueName("") .action((x, c) => c.copy(targetDir = x)) - .text("Target director to put files") + .text("Target directory to put files") opt[String]("dotFName") .abbr("df") @@ -50,6 +52,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case VerilatorSimulator => s"-FI ${fname}" // vcs pulls headers in with +incdir, doesn't have anything like verilator.h case VCSSimulator => "" + case _ => "" } } else { // do nothing otherwise fname @@ -82,26 +85,31 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { out.close() } def resources(sim: Simulator): Seq[String] = Seq( - "/testchipip/csrc/SimSerial.cc", - "/testchipip/csrc/SimDRAM.cc", - "/testchipip/csrc/mm.h", - "/testchipip/csrc/mm.cc", - "/testchipip/csrc/mm_dramsim2.h", - "/testchipip/csrc/mm_dramsim2.cc", - "/csrc/SimDTM.cc", - "/csrc/SimJTAG.cc", - "/csrc/remote_bitbang.h", - "/csrc/remote_bitbang.cc", "/vsrc/EICG_wrapper.v", - ) ++ (sim match { // simulator specific files to include - case VerilatorSimulator => Seq( - "/csrc/emulator.cc", - "/csrc/verilator.h", - ) - case VCSSimulator => Seq( - "/vsrc/TestDriver.v", - ) - }) + ) ++ (sim match { + case NotSimulator => Seq() + case _ => Seq( + "/testchipip/csrc/SimSerial.cc", + "/testchipip/csrc/SimDRAM.cc", + "/testchipip/csrc/mm.h", + "/testchipip/csrc/mm.cc", + "/testchipip/csrc/mm_dramsim2.h", + "/testchipip/csrc/mm_dramsim2.cc", + "/csrc/SimDTM.cc", + "/csrc/SimJTAG.cc", + "/csrc/remote_bitbang.h", + "/csrc/remote_bitbang.cc", + ) + }) ++ (sim match { // simulator specific files to include + case VerilatorSimulator => Seq( + "/csrc/emulator.cc", + "/csrc/verilator.h", + ) + case VCSSimulator => Seq( + "/vsrc/TestDriver.v", + ) + case _ => Seq() + }) def writeBootrom(): Unit = { firrtl.FileUtils.makeDirectory("./bootrom/")