diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index d25d4fa3..5d2ba60c 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -29,7 +29,7 @@ import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
 trait CanHaveHTIF { this: BaseSubsystem =>
   // Advertise HTIF if system can communicate with fesvr
   if (this match {
-    case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
+    case _: CanHavePeripheryTLSerial if (!p(SerialTLKey).isEmpty) => true
     case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
     case _ => false
   }) {