From 0593e92cb3ce35c85f31c3a45c09146a273aab78 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 Feb 2021 02:11:18 -0800 Subject: [PATCH 1/4] Passing MBus clock frequency to SimDRAM --- generators/chipyard/src/main/scala/HarnessBinders.scala | 3 ++- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 2 ++ generators/testchipip | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 02ab3732..588878d5 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -143,7 +143,8 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => val memSize = p(ExtMem).get.master.size val lineSize = p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)).suggestName("simdram") + val clockFreq = p(MemoryBusKey).dtsFrequency.get + val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, edge.bundle)).suggestName("simdram") mem.io.axi <> port.bits mem.io.clock := port.clock mem.io.reset := port.reset diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 73c2b006..a70ae4df 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -45,6 +45,8 @@ class AbstractConfig extends Config( new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) + new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus + new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) diff --git a/generators/testchipip b/generators/testchipip index 6572beb0..f2705592 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6572beb03bc6eb0575269eaf4cc960b72b3ddef3 +Subproject commit f27055929a2d4c091bfe10c3b64761e281844a2b From c85ffd2a59397fc6e7495527772202589fde43a3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 Feb 2021 03:14:48 -0800 Subject: [PATCH 2/4] Add support for manually adjusting DRAM latency with a ShiftQueue --- .../src/main/scala/HarnessBinders.scala | 24 +++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 588878d5..5428e342 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -1,7 +1,8 @@ package chipyard.harness import chisel3._ -import chisel3.experimental.{Analog, BaseModule} +import chisel3.util._ +import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} @@ -10,6 +11,7 @@ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.subsystem._ +import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ @@ -137,7 +139,7 @@ class WithSimAXIMem extends OverrideHarnessBinder({ } }) -class WithBlackBoxSimMem extends OverrideHarnessBinder({ +class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBinder({ (system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => { val p: Parameters = chipyard.iobinders.GetSystemParameters(system) (ports zip system.memAXI4Node.edges.in).map { case (port, edge) => @@ -146,6 +148,24 @@ class WithBlackBoxSimMem extends OverrideHarnessBinder({ val clockFreq = p(MemoryBusKey).dtsFrequency.get val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, edge.bundle)).suggestName("simdram") mem.io.axi <> port.bits + // Bug in Chisel implementation. See https://github.com/chipsalliance/chisel3/pull/1781 + def Decoupled[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { + require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") + val d = Wire(new DecoupledIO(chiselTypeOf(irr.bits))) + d.bits := irr.bits + d.valid := irr.valid + irr.ready := d.ready + d + } + if (additionalLatency > 0) { + withClockAndReset (port.clock, port.reset) { + mem.io.axi.aw <> ShiftQueue(Decoupled(port.bits.aw), additionalLatency) + mem.io.axi.w <> ShiftQueue(Decoupled(port.bits.w ), additionalLatency) + port.bits.b <> ShiftQueue(Decoupled(mem.io.axi.b), additionalLatency) + mem.io.axi.ar <> ShiftQueue(Decoupled(port.bits.ar), additionalLatency) + port.bits.r <> ShiftQueue(Decoupled(mem.io.axi.r), additionalLatency) + } + } mem.io.clock := port.clock mem.io.reset := port.reset } From 235b1e5dfd33b4a980a80463aec72ea0bd7a8648 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 Feb 2021 09:03:15 -0800 Subject: [PATCH 3/4] Give TraceGenConfigs an explicit mbus clock --- generators/chipyard/src/main/scala/config/TracegenConfigs.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index f9980bf6..3f9e27d1 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -11,6 +11,8 @@ class AbstractTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ + new chipyard.config.WithMemoryBusFrequency(100.0) ++ + new chipyard.config.WithPeripheryBusFrequency(100.0) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.groundtest.GroundTestBaseConfig) From 4c11e170b856407df2b7fb1c5f6e1c2e59887af6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 Feb 2021 00:47:10 -0800 Subject: [PATCH 4/4] Use series of pipe Queues instead of ShiftQueue for adding AXI4 memory delay --- .../chipyard/src/main/scala/HarnessBinders.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 5428e342..643b2065 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -159,11 +159,11 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind } if (additionalLatency > 0) { withClockAndReset (port.clock, port.reset) { - mem.io.axi.aw <> ShiftQueue(Decoupled(port.bits.aw), additionalLatency) - mem.io.axi.w <> ShiftQueue(Decoupled(port.bits.w ), additionalLatency) - port.bits.b <> ShiftQueue(Decoupled(mem.io.axi.b), additionalLatency) - mem.io.axi.ar <> ShiftQueue(Decoupled(port.bits.ar), additionalLatency) - port.bits.r <> ShiftQueue(Decoupled(mem.io.axi.r), additionalLatency) + mem.io.axi.aw <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.aw))((t, _) => Queue(t, 1, pipe=true)) + mem.io.axi.w <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.w ))((t, _) => Queue(t, 1, pipe=true)) + port.bits.b <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.b))((t, _) => Queue(t, 1, pipe=true)) + mem.io.axi.ar <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.ar))((t, _) => Queue(t, 1, pipe=true)) + port.bits.r <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.r))((t, _) => Queue(t, 1, pipe=true)) } } mem.io.clock := port.clock