wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Set number of idbits correctly for fpga ddr

Browse Source
This commit is contained in:
Jerry Zhao
2023-05-15 00:04:12 -07:00
parent f4739be632
commit 57f5168408
3 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/src/main/scala/vc707/TestHarness.scala
View File

@@ -78,7 +78,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
val ddrNode = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLL, true)).overlayOutput.ddr
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
sourceId = IdRange(0, 64)
sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
)))))
ddrNode := ddrClient