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Set number of idbits correctly for fpga ddr

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This commit is contained in:
Jerry Zhao
2023-05-15 00:04:12 -07:00
parent f4739be632
commit 57f5168408
3 changed files with 3 additions and 3 deletions
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2
fpga/src/main/scala/arty100t/Harness.scala
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@@ -40,7 +40,7 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
name = "chip_ddr",
sourceId = IdRange(0, 64)
sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
)))))
val ddrBlockDuringReset = LazyModule(new TLBlockDuringReset(4))
ddrOverlay.overlayOutput.ddr := ddrBlockDuringReset.node := ddrClient