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Remove MultiClockHarnessAXIMem

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Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.

Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
This commit is contained in:
Jerry Zhao
2023-09-16 09:47:47 -07:00
parent 174ebc50b7
commit 57ee757016
7 changed files with 10 additions and 137 deletions
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12
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -302,18 +302,6 @@ class FireSimCVA6Config extends Config(
new WithFireSimConfigTweaks ++
new chipyard.CVA6Config)
//**********************************************************************************
//* Multiclock Configurations
//*********************************************************************************/
class FireSimMulticlockAXIOverSerialConfig extends Config(
new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial
new WithDefaultFireSimBridges ++
new testchipip.WithBlockDevice(false) ++ // disable blockdev
new WithDefaultMemModel ++
new WithFireSimDesignTweaks ++ // don't inherit firesim clocking
new chipyard.MulticlockAXIOverSerialConfig
)
//**********************************************************************************
// System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations
// - Requires MTModels and MCRams mixins as prefixes to the platform config