Remove MultiClockHarnessAXIMem

Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.

Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -12,7 +12,6 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
                                                                    // NOTE: This only simulates properly in VCS
-  new chipyard.harness.WithSimAXIMemOverSerialTL ++                // Attach SimDRAM to serial-tl port
 
   //==================================
   // Set up tiles

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -96,29 +96,6 @@ class MulticlockRocketConfig extends Config(
   new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
   new chipyard.config.AbstractConfig)
 
-// DOC include start: MulticlockAXIOverSerialConfig
-class MulticlockAXIOverSerialConfig extends Config(
-  new chipyard.config.WithSystemBusFrequency(250) ++
-  new chipyard.config.WithPeripheryBusFrequency(250) ++
-  new chipyard.config.WithMemoryBusFrequency(250) ++
-  new chipyard.config.WithFrontBusFrequency(50) ++
-  new chipyard.config.WithTileFrequency(500, Some(1)) ++
-  new chipyard.config.WithTileFrequency(250, Some(0)) ++
-
-  new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++
-  new testchipip.WithAsynchronousSerialSlaveCrossing ++
-  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(
-    AsynchronousCrossing().depth,
-    AsynchronousCrossing().sourceSync) ++
-
-  new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
-  new testchipip.WithSerialTLBackingMemory ++       // remove axi4 mem port in favor of SerialTL memory
-
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
-  new chipyard.config.AbstractConfig)
-// DOC include end: MulticlockAXIOverSerialConfig
-
 class CustomIOChipTopRocketConfig extends Config(
   new chipyard.example.WithCustomChipTop ++
   new chipyard.example.WithCustomIOCells ++

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -1,7 +1,7 @@
 package chipyard.example
 
 import chisel3._
-
+import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 
 import org.chipsalliance.cde.config.{Field, Parameters}
@@ -41,30 +41,19 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
   // Serialized TL
   val sVal = p(SerialTLKey).get
   val serialTLManagerParams = sVal.serialTLManagerParams.get
-  val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
   require(serialTLManagerParams.isMemoryDevice)
-  val memFreq = axiDomainParams.getMemFrequency(lazyDut.system)
 
   withClockAndReset(clock, reset) {
     val serial_bits = dut.serial_tl_pad.bits
-    dut.serial_tl_pad.clock := clock
-    val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM(
+    if (DataMirror.directionOf(dut.serial_tl_pad.clock) == Direction.Input) {
+      dut.serial_tl_pad.clock := clock
+    }
+    val harnessRAM = TSIHarness.connectRAM(
       lazyDut.system.serdesser.get,
       serial_bits,
-      clock,
       reset)
-    io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset)
+    io.success := SimTSI.connect(Some(harnessRAM.module.io.tsi), clock, reset)
 
-    // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
-    (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
-      val memSize = serialTLManagerParams.memParams.size
-      val memBase = serialTLManagerParams.memParams.base
-      val lineSize = p(CacheBlockBytes)
-      val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
-      mem.io.axi <> axi_port.bits
-      mem.io.clock := axi_port.clock
-      mem.io.reset := axi_port.reset
-    }
   }
 
   // JTAG

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -128,46 +128,6 @@ class WithSimAXIMem extends OverrideHarnessBinder({
   }
 })
 
-class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
-  (system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
-    implicit val p = chipyard.iobinders.GetSystemParameters(system)
-
-    p(SerialTLKey).map({ sVal =>
-      val serialTLManagerParams = sVal.serialTLManagerParams.get
-      val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
-      require(serialTLManagerParams.isMemoryDevice)
-
-      val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
-
-      ports.map({ port =>
-// DOC include start: HarnessClockInstantiatorEx
-        val memOverSerialTLClock = th.harnessClockInstantiator.requestClockHz("mem_over_serial_tl_clock", memFreq)
-        val serial_bits = port.bits
-        port.clock := th.harnessBinderClock
-        val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM(
-          system.serdesser.get,
-          serial_bits,
-          memOverSerialTLClock,
-          th.harnessBinderReset)
-        // DOC include end: HarnessClockInstantiatorEx
-        val success = SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), th.harnessBinderClock, th.harnessBinderReset.asBool)
-        when (success) { th.success := true.B }
-
-        // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
-        (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
-          val memSize = serialTLManagerParams.memParams.size
-          val memBase = serialTLManagerParams.memParams.base
-          val lineSize = p(CacheBlockBytes)
-          val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
-          mem.io.axi <> axi_port.bits
-          mem.io.clock := axi_port.clock
-          mem.io.reset := axi_port.reset
-        }
-      })
-    })
-  }
-})
-
 class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBinder({
   (system: CanHaveMasterAXI4MemPort, th: HasHarnessInstantiators, ports: Seq[ClockedAndResetIO[AXI4Bundle]]) => {
     val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
@@ -305,7 +265,9 @@ class WithSimTSIOverSerialTL extends OverrideHarnessBinder({
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
     ports.map({ port =>
       val bits = port.bits
-      port.clock := th.harnessBinderClock
+      if (DataMirror.directionOf(port.clock) == Direction.Input) {
+        port.clock := th.harnessBinderClock
+      }
       val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
       val success = SimTSI.connect(Some(ram.module.io.tsi), th.harnessBinderClock, th.harnessBinderReset.asBool)
       when (success) { th.success := true.B }