Merge remote-tracking branch 'origin/main' into tcip-bump
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@@ -29,7 +29,7 @@ import chipyard.{ExtTLMem}
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* @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
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* @param contentFileName the path to the BootROM image
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*/
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class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => {
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class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10000) extends Config((site, here, up) => {
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case BootROMLocated(x) => up(BootROMLocated(x), site)
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.map(_.copy(
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address = address,
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@@ -66,6 +66,15 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
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}
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})
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class WithRocketCacheRowBits(rowBits: Int = 64) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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dcache = tp.tileParams.dcache.map(_.copy(rowBits = rowBits)),
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icache = tp.tileParams.icache.map(_.copy(rowBits = rowBits))
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))
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}
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})
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class WithRocketICacheScratchpad extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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Submodule generators/testchipip updated: 23d6a3805f...e1bed32643
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