Fix broken GCD example
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@@ -40,12 +40,12 @@ Top-level traits specify that the ``DigitalTop`` has been parameterized to read
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Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``DigitalTop`` being used by Chipyard.
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Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``DigitalTop`` to instantiate an additional port and concretely connect it to the GCD module.
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Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph.
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
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:language: scala
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:start-after: DOC include start: GCD lazy trait
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:end-before: DOC include end: GCD imp trait
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:end-before: DOC include end: GCD lazy trait
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These traits are added to the default ``DigitalTop`` in Chipyard.
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@@ -79,13 +79,7 @@ Register routers have a TileLink node simply named "node", which we can hook up
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This will automatically add address map and device tree entries for the peripheral.
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Also observe how we have to place additional AXI4 buffers and converters for the AXI4 version of this peripheral.
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For peripherals which instantiate a concrete module, or which need to be connected to concrete IOs or wires, a matching concrete trait is necessary. We will make our GCD example output a ``gcd_busy`` signal as a top-level port to demonstrate. In the concrete module implementation trait, we instantiate the top level IO (a concrete object) and wire it to the IO of our lazy module.
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.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala
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:language: scala
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:start-after: DOC include start: GCD imp trait
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:end-before: DOC include end: GCD imp trait
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Peripherals which expose I/O can use `InModuleBody` to punch their I/O to the `DigitalTop` module.
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Constructing the DigitalTop and Config
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--------------------------------------
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