NOT WORKING: VCU118 Commit
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51
fpga/src/main/scala/vcu118/Configs.scala
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51
fpga/src/main/scala/vcu118/Configs.scala
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// See LICENSE for license details.
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package chipyard.fpga.vcu118
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.mockaon._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.pwm._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.i2c._
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import sifive.fpgashells.shell.{DesignKey}
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import chipyard.{BuildTop}
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class WithChipyardBuildTop extends Config((site, here, up) => {
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//case DesignKey => { (p:Parameters) => p(BuildTop)(p) }
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case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) }
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})
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class WithBringupUARTs extends Config((site, here, up) => {
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case PeripheryUARTKey => List(
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UARTParams(address = BigInt(0x64000000L)),
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UARTParams(address = BigInt(0x64003000L)))
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})
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class FakeBringupConfig extends Config(
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new WithUARTConnection1 ++
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new WithBringupUARTs ++
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new WithChipyardBuildTop ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.With1TinyCore ++
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNoMemPort ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
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new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
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new freechips.rocketchip.subsystem.WithJtagDTM ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
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new freechips.rocketchip.system.BaseConfig)
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