diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala
index 205135a2..e6cfa8cb 100644
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -15,6 +15,9 @@ import barstools.iocell.chisel._
 
 case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p))
 
+trait HasReferenceClockFreq {
+  var refClockFreqMHz: Option[Double] = None
+}
 
 /**
  * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
@@ -24,7 +27,7 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters)
  */
 
 class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
-    with HasTestHarnessFunctions with HasIOBinders {
+    with HasTestHarnessFunctions with HasReferenceClockFreq with HasIOBinders {
   // The system module specified by BuildSystem
   lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system")
 
diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
index 65346ea6..00c07417 100644
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -47,12 +47,6 @@ case object ClockingSchemeKey extends Field[ChipTop => Unit](ClockingSchemeGener
   */
 case object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty)
 case object DefaultClockFrequencyKey extends Field[Double]()
-case object ReferenceClockTrackerKey extends Field[ReferenceClockTracker](new ReferenceClockTracker)
-class ReferenceClockTracker {
-  private var _refFreqMHz: Option[Double] = None
-  def set(freqMHz: Double): Unit = { _refFreqMHz = Some(freqMHz) }
-  def get: Option[Double] = { _refFreqMHz }
-}
 
 class ClockNameMatchesAssignment(name: String, fMHz: Double) extends Config((site, here, up) => {
   case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
@@ -106,7 +100,8 @@ object ClockingSchemeGenerators {
       val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock")
       chiptop.iocells ++= clockIOCell
 
-      p(ReferenceClockTrackerKey).set(dividerOnlyClkGenerator.module.referenceFreq)
+      // set the reference clock used
+      chiptop.refClockFreqMHz = Some(dividerOnlyClkGenerator.module.referenceFreq)
 
       referenceClockSource.out.unzip._1.map { o =>
         o.clock := clock_wire
diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala
index c0c28088..c02df03e 100644
--- a/generators/chipyard/src/main/scala/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/TestHarness.scala
@@ -23,6 +23,7 @@ trait HasTestHarnessFunctions {
 }
 
 trait HasHarnessSignalReferences {
+  // clock/reset of the chiptop reference clock (can be different than the implicit harness clock/reset)
   def harnessClock: Clock
   def harnessReset: Reset
   def dutReset: Reset
@@ -81,15 +82,25 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
     val success = Output(Bool())
   })
 
+  val harnessClock = Wire(Clock())
+  val harnessReset = Wire(Reset())
+
   val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
-  val dut = Module(lazyDut.module)
+  withClockAndReset(harnessClock, harnessReset) {
+    val dut = Module(lazyDut.module)
+  }
   io.success := false.B
 
-  val (harnessClock, harnessReset, dutReset) = {
-    val freqMHz = p(ReferenceClockTrackerKey).get.getOrElse(100.0) // default to 100MHz
-    val bundle = p(HarnessClockInstantiatorKey).getClockBundleWire("implicit_harness_clock", freqMHz*1000000.0)
-    (bundle.clock, WireInit(bundle.reset), bundle.reset.asAsyncReset)
+  val freqMHz = lazyDut match {
+    case d: HasReferenceClockFreq => d.refClockFreqMHz.getOrElse(p(DefaultClockFrequencyKey))
+    case _ => p(DefaultClockFrequencyKey)
   }
+  val refClkBundle = p(HarnessClockInstantiatorKey).getClockBundleWire("chiptop_reference_clock", freqMHz * (1000 * 1000))
+
+  harnessClock := refClkBundle.clock
+  harnessReset := WireInit(refClkBundle.reset)
+  val dutReset = refClkBundle.reset.asAsyncReset
+
   val success = io.success
 
   lazyDut match { case d: HasTestHarnessFunctions =>
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index cbb8f06b..45f016bf 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -215,11 +215,11 @@ class LBWIFRocketConfig extends Config(
 
 class MulticlockAXIOverSerialConfig extends Config(
   new chipyard.config.WithSystemBusFrequencyAsDefault ++
-  new chipyard.config.WithSystemBusFrequency(500) ++
-  new chipyard.config.WithPeripheryBusFrequency(500) ++
-  new chipyard.config.WithMemoryBusFrequency(500) ++
+  new chipyard.config.WithSystemBusFrequency(250) ++
+  new chipyard.config.WithPeripheryBusFrequency(250) ++
+  new chipyard.config.WithMemoryBusFrequency(250) ++
   new chipyard.config.WithFrontBusFrequency(50) ++
-  new chipyard.config.WithTileFrequency(1000, Some(1)) ++
+  new chipyard.config.WithTileFrequency(500, Some(1)) ++
   new chipyard.config.WithTileFrequency(250, Some(0)) ++
 
   new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++